US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 106

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 3 Exception Handling
Bit 1—Timer C Interrupt Enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
0
1
Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
0
1
For details of SCI3 interrupt control, see section 10.2.6 Serial control register 3 (SCR3).
Interrupt Request Register 1 (IRR1)
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC, IRQ
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Rev. 8.00 Mar. 09, 2010 Page 84 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Note: * Only a write of 0 for flag clearing is possible
Description
Disables timer C interrupt requests
Enables timer C interrupt requests
Description
Disables asynchronous event counter interrupt requests
Enables asynchronous event counter interrupt requests
4
, IRQ
R/(W) *
IRRTA
7
0
3
, IRQ
1
, or IRQ
⎯
⎯
W
6
0
interrupt is requested. The flags are not cleared
⎯
⎯
5
1
IRRI4
R/(W) *
4
0
IRRI3
R/(W) *
3
0
IRREC2
R/(W) *
2
0
R/(W) *
IRRI1
1
0
(initial value)
(initial value)
R/(W) *
IRRI0
0
0