US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 462

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
14.3.2
LVDR (Reset by Low Voltage Detect) Circuit:
Figure 14.3 shows the timing of the LVDR function. The LVDR enters the module-standby state
after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait
for 150 μs (t
stabilized, based on overflow of LVDNT, etc., then set the LVDRE bit in LVDCR to 1. After that,
the output settings of ports must be made. To cancel the low-voltage detection circuit, first the
LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and
LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur.
When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.3 V), the LVDR
clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock (φ) cycles, and
then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in
LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below V
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
Rev. 8.00 Mar. 09, 2010 Page 440 of 658
REJ09B0042-0800
RES
Vcc
PSS-reset
signal
OVF
Internal reset
signal
Low-Voltage Detection Circuit
LVDON
Vpor
t
PWON
Figure 14.2 Operational Timing of Power-On Reset Circuit
) until the reference voltage and the low-voltage-detection power supply have
PSS counter starts
131,072 cycles
Reset released
LVDRmin
= 1.0 V and then rises from that
Vss
Vss