US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 157

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.4.2
Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0, or WKP7 to WKP0) or
by input at the RES pin.
• Clearing by interrupt
• Clearing by RES input
5.4.3
The wait time is the same as for standby mode; see section 5.3.3, Oscillator Stabilization Time
after Standby Mode is Cleared.
5.4.4
See section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.
When watch mode is cleared by interrupt, the mode to which a transition is made depends on
the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are
cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition
is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the
transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a
stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception
handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in section
5.3.2, Clearing Standby Mode.
Clearing Watch Mode
Oscillator StabilizationTime after Watch Mode Is Cleared
Notes on External Input Signal Changes before/after Watch Mode
Rev. 8.00 Mar. 09, 2010 Page 135 of 658
Section 5 Power-Down Modes
REJ09B0042-0800