US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 80

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US38024-BAG1

Manufacturer Part Number
US38024-BAG1
Description
DEV EVALUATION KIT H8/38024
Manufacturer
Renesas Electronics America
Series
H8®r
Type
MCUr
Datasheet

Specifications of US38024-BAG1

Contents
2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
For Use With/related Products
H8/38024
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 2 CPU
Rev. 8.00 Mar. 09, 2010 Page 58 of 658
REJ09B0042-0800
CPU state
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
A state in which some
or all of the chip
functions are stopped
to conserve power
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
The CPU is initialized
Program halt state
execution state
Figure 2.14 CPU Operation States
handling state
Reset state
Exception-
Program
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Sleep (medium-speed)
(medium speed) mode
(high speed) mode
Sleep (high-speed)
Subactive mode
Subsleep mode
Standby mode
Watch mode
Active
Active
mode
mode
Low-power
modes

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