US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 307

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register Configuration
Table 9.11 shows the register configuration of timer G.
Table 9.11 Timer G Registers
Name
Timer control register G
Timer counter G
Input capture register GF
Input capture register GR
Clock stop register 1
9.5.2
Timer Counter G (TCG)
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer * . In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
Bit:
Initial value:
Read/Write:
Register Descriptions
TCG7
⎯
7
0
TCG6
⎯
6
0
Abbr.
TMG
TCG
ICRGF
ICRGR
CKSTPR1
TCG5
⎯
5
0
TCG4
⎯
4
0
R/W
R/W
—
R
R
R/W
Rev. 8.00 Mar. 09, 2010 Page 285 of 658
TCG3
⎯
3
0
H'00
H'00
H'00
H'00
H'FF
Initial Value
TCG2
⎯
2
0
TCG1
REJ09B0042-0800
Section 9 Timers
⎯
1
0
Address
H'FFBC
—
H'FFBD
H'FFBE
H'FFFA
TCG0
⎯
0
0