US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 148

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 5 Power-Down Modes
Bit 3—Low Speed on Flag (LSON)
This bit chooses the system clock (φ) or subclock (φ
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
0
1
Bit 2—Reserved
Bit 2 is reserved: it is always read as 1 and cannot be modified.
Bits 1 and 0—Active (Medium-Speed) Mode Clock Select (MA1, MA0)
Bits 1 and 0 choose φ
speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-
speed) mode or subactive mode.
Bit 1
MA1
0
0
1
1
System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5—Reserved
These bits are reserved; they are always read as 1, and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 126 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Description
The CPU operates on the system clock (φ)
The CPU operates on the subclock (φ
Bit 0
MA0
0
1
0
1
⎯
⎯
7
1
osc
/128, φ
Description
φ
φ
φ
φ
osc
osc
osc
osc
osc
⎯
⎯
6
1
/16
/32
/64
/128
/64, φ
osc
/32, or φ
⎯
⎯
5
1
NESEL
osc
R/W
4
1
SUB
/16 as the operating clock in active (medium-
SUB
)
) as the CPU operating clock when watch
DTON
R/W
3
0
MSON
R/W
2
0
R/W
SA1
1
0
(initial value)
(initial value)
SA0
R/W
0
0