US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 404

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 10 Serial Communication Interface
Consequently, the receive margin in asynchronous mode can be expressed as shown in equation
(1).
Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.
Rev. 8.00 Mar. 09, 2010 Page 382 of 658
REJ09B0042-0800
Internal
basic clock
Receive data
(RXD32)
Synchronization
sampling timing
Data sampling
timing
where
When D = 0.5 and F = 0,
M = {0.5 – 1/(2 × 16)} × 100 [%]
M ={(0.5 –
= 46.875%
Figure 10.16 Receive Data Sampling Timing in Asynchronous Mode
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
2N
1
0
8 clock pulses
Start bit
) –
D – 0.5
N
16 clock pulses
7
– (L – 0.5) F} × 100 [%]
15 0
D0
.... Equation (2)
..... Equation (1)
7
15 0
D1