US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 257

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US38024-BAG1

Manufacturer Part Number
US38024-BAG1
Description
DEV EVALUATION KIT H8/38024
Manufacturer
Renesas Electronics America
Series
H8®r
Type
MCUr
Datasheet

Specifications of US38024-BAG1

Contents
2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
For Use With/related Products
H8/38024
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
8.10
8.10.1
Port A is a 4-bit I/O port, configured as shown in figure 8.9.
8.10.2
Table 8.26 shows the port A register configuration.
Table 8.26 Port A Registers
Name
Port data register A
Port control register A
Port Data Register A (PDRA)
PDRA is an 8-bit register that stores data for port A pins PA
PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If
port A is read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
Bit
Initial value
Read/Write
Overview
Register Configuration and Description
Port A
7
1
Figure 8.9 Port A Pin Configuration
6
1
Port A
Abbr.
PDRA
PCRA
5
1
4
1
Rev. 8.00 Mar. 09, 2010 Page 235 of 658
PA
PA
PA
PA
R/W
R/W
W
R/W
3
2
1
0
PA
3
/COM
/COM
/COM
/COM
3
0
to PA
3
4
3
2
1
0
. If port A is read while
R/W
PA
Initial Value
H'F0
H'F0
2
0
2
Section 8 I/O Ports
R/W
REJ09B0042-0800
PA
1
0
1
Address
H'FFDD
H'FFED
R/W
PA
0
0
0

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