US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 308

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US38024-BAG1

Manufacturer Part Number
US38024-BAG1
Description
DEV EVALUATION KIT H8/38024
Manufacturer
Renesas Electronics America
Series
H8®r
Type
MCUr
Datasheet

Specifications of US38024-BAG1

Contents
2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
For Use With/related Products
H8/38024
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 9 Timers
Input Capture Register GF (ICRGF)
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
ICRGF is initialized to H'00 upon reset.
Input Capture Register GR (ICRGR)
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
ICRGR is initialized to H'00 upon reset.
Rev. 8.00 Mar. 09, 2010 Page 286 of 658
REJ09B0042-0800
Bit:
Initial value:
Read/Write:
Bit:
Initial value:
Read/Write:
ICRGR7
ICRGF7
R
R
7
0
7
0
SUB
SUB
ICRGR6
ICRGF6
(when the noise canceler is not used).
(when the noise canceler is not used).
R
R
6
0
6
0
ICRGR5
ICRGF5
R
R
5
0
5
0
ICRGR4
ICRGF4
R
R
4
0
4
0
ICRGR3
ICRGF3
R
R
3
0
3
0
ICRGR2
ICRGF2
R
R
2
0
2
0
ICRGR1
ICRGF1
R
R
1
0
1
0
ICRGR0
ICRGF0
R
R
0
0
0
0

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