ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 813

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

41.5.9
41.5.10
32058J–AVR32–04/11
HMatrix
ADC
4. Peripheral Bus A maximum frequency is 33MHz instead of 66MHz.
5.
6.
7. If the BOD level is higher than VDDCORE, the part is constantly under reset
8. System Timer mask (Bit 16) of the PM CPUMASK register is not available.
1. HMatrix fixed priority arbitration does not work
1.
2.
3. Sleep Mode activation needs additional A to D conversion
Fix/Workaround
In PLL0/1 Control register, the bit 7 should be set in order to prevent unexpected behaviour.
Fix/Workaround
Do not set PBA frequency higher than 33 MHz.
In sleep mode stop all PCx pins will be controlled by GPIO module instead of oscillators.
This can cause drive contention on the XINx in worst case.
Fix/Workaround
Before entering stop mode set all PCx pins to input and GPIO controlled.
Fix/Workaround
Do not set the HSB/CPU speed higher than 50MHz when the firmware generate exceptions.
If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will
be in constant reset.
Fix/Workaround
Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than
VDDCORE max and disable the BOD.
Fix/Workaround
Do not use this bit.
Fixed priority arbitration does not work.
Fix/Workaround
Use Round-Robin arbitration instead.
The ADC does not work properly when more than one channel is enabled.
Fix/Workaround
Do not use the ADC with more than one channel enabled at a time.
The OVRE flag does not clear properly if read simultaneously to an end of conversion.
Fix/Workaround
None.
PCx pins go low in stop mode
On some rare parts, the maximum HSB and CPU speed is 50MHz instead of 66MHz.
ADC possible miss on DRDY when disabling a channel
ADC OVRE flag sometimes not reset on Status Register read
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