ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 512

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.7.2.4
30.7.2.5
Figure 30-14. Endpoint Activation Algorithm
32058J–AVR32–04/11
Endpoint Reset
Endpoint Activation
An endpoint can be reset at any time by setting its EPRSTX bit in the UERST register. This is
recommended before using an endpoint upon hardware reset or when a USB bus reset has
been received. This resets:
Note that the interrupt sources located in the UESTAX register are not cleared when a USB bus
reset has been received.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle sequence as an answer to
the CLEAR_FEATURE USB request. This can be achieved by setting the RSTDT bit (by setting
the RSTDTS bit).
In the end, the firmware has to clear the EPRSTX bit to complete the reset operation and to start
using the FIFO.
The endpoint is maintained inactive and reset (see
details) as long as it is disabled (EPENX = 0). The Data Toggle Sequence bit-field (DTSEQ) is
also reset.
The algorithm represented on
As long as the endpoint is not correctly configured (CFGOK = 0), the controller does not
acknowledge the packets sent by the host to this endpoint.
The CFGOK bit is set by hardware only if the configured size and number of banks are correct
compared to their maximal allowed values for the endpoint (see
the maximal FIFO size (i.e. the DPRAM size).
•the internal state machine of this endpoint;
•the receive and transmit bank FIFO counters;
•all the registers of this endpoint (UECFGX, UESTAX, UECONX), except its configuration
(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and its Data Toggle Sequence bit-field (DTSEQ).
Yes
EPENX = 1
CFGOK ==
Activation
UECFGX
Activated
Endpoint
Endpoint
EPTYPE
EPSIZE
ALLOC
EPDIR
EPBK
1?
No
ERROR
Figure 30-14
Enable the endpoint.
Configure the endpoint:
Allocate the configured DPRAM
banks.
Test if the endpoint configuration
is correct.
must be followed in order to activate an endpoint.
- type;
- direction;
- size;
- number of banks.
Section 30.7.2.4 on page 512
Table 30-1 on page
AT32UC3A
497) and to
for more
512