ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 453

KIT EVAL FOR AT32UC3A0

ATEVK1105

Manufacturer Part Number
ATEVK1105
Description
KIT EVAL FOR AT32UC3A0
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets

Specifications of ATEVK1105

Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A0512
Processor Series
AVR
Data Bus Width
32 bit
Interface Type
USART, TWI, USB, SPI, Ethernet
Operating Supply Voltage
3.3 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A0512
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
29.6.1.7
32058J–AVR32–04/11
Receiving Frames
When a frame is received and the receive circuits are enabled, the MACB checks the address
and, in the following cases, the frame is written to system memory:
The register receive buffer queue pointer points to the next entry (see
and the MACB uses this as the address in system memory to write the frame to. Once the frame
has been completely and successfully received and written to system memory, the MACB then
updates the receive buffer descriptor entry with the reason for the address match and marks the
area as being owned by software. Once this is complete an interrupt receive complete is set.
Software is then responsible for handling the data in the buffer and then releasing the buffer by
writing the ownership bit back to 0.
If the MACB is unable to write the data at a rate to match the incoming frame, then an interrupt
receive overrun is set. If there is no receive buffer available, i.e., the next buffer is still owned by
software, the interrupt receive buffer not available is set. If the frame is not successfully
received, a statistic register is incremented and the frame is discarded without informing
software.
• if it matches one of the four specific address registers.
• if it matches the hash address function.
• if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.
• if the MACB is configured to copy all frames.
• if the EAM is asserted before four words have been loaded into the receive FIFO.
Table 29-1 on page
AT32UC3A
440)
453

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