ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 266

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 25-8. Transmitter Block Diagram
25.7.3
32058J-AVR32-04/11
Transmitter Clock
RX_FRAME_SYNC
Receiver Operations
TX_FRAME_SYNC
TFMR.DATLEN
TCMR.STTDLY
TFMR.FSDEN
Selector
Start
A received frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured setting the Receive Clock Mode Register (RCMR).
“25.7.4” on page 267.
The frame synchronization is configured setting the Receive Frame Mode Register (RFMR).
Section “25.7.5” on page 269.
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the RCMR. The data is transferred from the shift register depending on the data for-
mat selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the sta-
tus flag RXRDY is set in SR and the data can be read in the receiver holding register. If another
transfer occurs before read of the RHR register, the status flag OVERUN is set in SR and the
receiver shift register is transferred in the RHR register.
TFMR.MSBF
THR
Transmit Shift Register
TFMR.DATDEF
0
1
TSHR
0
1
TFMR.FSLEN
TCMR.STTDLY
TFMR.DATNB
TFMR.FSDEN
CR.TXEN
CR.TXDIS
SR.TXEN
AT32UC3A
TX_DATA
See Section
See
266