ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 284

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.9.6
Name:
Access Type:
Offset:
Reset value:
• FSLENHI: Transmit Frame Sync Length High part
The four MSB of the FSLEN bitfield.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
• FSDEN: Frame Sync Data Enable
0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.
1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
• FSOS: Transmit Frame Sync Output Selection
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync
Data Register if FSDEN is 1. Note: The four most significant bits fo this bitfield are in the FSLENHI bitfield.
32058J-AVR32-04/11
FSDEN
MSBF
FSEDGE
0x6-0x7
31
23
15
FSOS
–
7
0x0
0x1
0x2
0x3
0x4
0x5
0x0
0x1
Transmit Frame Mode Register
Selected Transmit Frame Sync Signal
None
Negative Pulse
Positive Pulse
Driven Low during data transfer
Driven High during data transfer
Toggling at each start of data transfer
Reserved
Frame Sync Edge Detection
Positive Edge Detection
Negative Edge Detection
30
22
14
TFMR
Read/Write
0x1C
0x00000000
–
6
–
FSLENHI
DATDEF
FSOS
29
21
13
–
5
28
20
12
–
4
27
19
11
–
3
DATLEN
26
18
10
–
2
FSLEN
DATNB
25
17
TX_FRAME_SYNC Pin
–
9
1
AT32UC3A
Undefined
Input-only
Output
Output
Output
Output
Output
FSEDGE
24
16
8
0
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