ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 515

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.7.2.11.2 Control Write
Figure 30-15. Control Write
30.7.2.11.3 Control Read
Figure 30-16. Control Read
32058J–AVR32–04/11
USB Bus
RXSTPI
RXOUTI
TXINI
Wr Enable
HOST
Wr Enable
CPU
USB Bus
RXSTPI
RXOUTI
TXINI
SETUP
SETUP
Figure 30-15
necessarily send a NAK on the first IN token:
Figure 30-16
neous write requests from the CPU and the USB host.
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all the data written by the CPU is lost and clearing
TXINI has no effect.
The firmware checks if the transmission or the reception is complete.
SETUP
HW
•the Received OUT Data interrupt (RXOUTI) which is raised when a new OUT packet is
•the Transmitted IN Data interrupt (TXINI) which is raised when the current bank is ready to
•if the firmware knows the exact number of descriptor bytes that must be read, it can then
•or it can read the bytes and wait for the NAKed IN interrupt (NAKINI) which tells that all the
SETUP
received and which shall be cleared by firmware to acknowledge the packet and to free the
bank;
accept a new IN packet and which shall be cleared by firmware to send the packet.
anticipate the status stage and send a zero-length packet after the next IN token;
bytes have been sent by the host and that the transaction is now in the status stage.
HW
SW
SW
SW
shows a control read transaction. The USB controller has to manage the simulta-
shows a control write transaction. During the status stage, the controller will not
IN
HW
OUT
HW
DATA
SW
SW
DATA
IN
OUT
HW
SW
OUT
NAK
NAK
IN
STATUS
STATUS
SW
OUT
HW
IN
AT32UC3A
SW
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