ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 324

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.7.4.6
Figure 26-25. Framing Error Status
26.7.4.7
32058J–AVR32–04/11
Framing Error
Transmit Break
Baud Rate
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of
a received character is detected at level 0. This can occur if the receiver and the transmitter are
fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (CSR). The
FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is
cleared by writing the Control Register (CR) with the RSTSTA bit at 1.
The user can request the transmitter to generate a break condition on the TXD line. A break con-
dition drives the TXD line low during at least one complete character. It appears the same as a
0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the
TXD line at least during one character until the user requests the break condition to be removed.
A break is transmitted by writing the Control Register (CR) with the STTBRK bit at 1. This can be
performed at any time, either while the transmitter is empty (no character in either the Shift Reg-
ister or in THR) or when a character is being transmitted. If a break is requested while a
character is being shifted out, the character is first completed before the TXD line is held low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of
the break is completed.
The break condition is removed by writing CR with the STPBRK bit at 1. If the STPBRK is
requested before the end of the minimum break duration (one character, including start, data,
parity and stop bits), the transmitter ensures that the break condition completes.
The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK
commands are taken into account only if the TXRDY bit in CSR is at 1 and the start of the break
condition clears the TXRDY and TXEMPTY bits as if a character is processed.
Writing CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All
STPBRK commands requested without a previous STTBRK command are ignored. A byte writ-
ten into the Transmit Holding Register while a break is pending, but not started, is ignored.
FRAME
RXRDY
US_CR
Clock
Write
RXD
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
RSTSTA = 1
AT32UC3A
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