ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 643

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

31.6.1.4
31.6.1.5
32058J–AVR32–04/11
TC Operating Modes
Trigger
Figure 31-3. Clock Control
Each channel can independently operate in two different modes:
• Capture Mode provides measurement on signals.
• Waveform Mode provides wave generation.
The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register.
In Capture Mode, TIOA and TIOB are configured as inputs.
In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not
selected to be the external trigger.
A trigger resets the counter and starts the counter clock. Three types of triggers are common to
both modes, and a fourth external trigger is available to each mode.
The following triggers are common to both modes:
• Software Trigger: Each channel has a software trigger, available by setting SWTRG in CCR.
• SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the
• Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the
The channel can also be configured to have an external trigger. In Capture Mode, the external
trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event
can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external
event can then be programmed to perform a trigger by setting ENETRG in CMR.
(LDBSTOP = 1 in CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in CMR).
The start and the stop commands have effect only if the clock is enabled.
same effect as a software trigger. The SYNC signals of all channels are asserted
simultaneously by writing BCR (Block Control) with SYNC set.
counter value matches the RC value if CPCTRG is set in CMR.
Selected
Counter
Clock
Clock
Q
R
S
Trigger
CLKSTA
Q
CLKEN
S
R
Event
Stop
CLKDIS
Disable
Event
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