ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 208

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.8.2
Name:
Access Type:
•
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
•
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
•
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
•
0 = The SPI operates at MCK.
1 = The SPI operates at MCK/32.
•
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
•
0 = Local loopback path disabled.
1 = Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing in Master Mode only. MISO is internally connected to
MOSI.
32058J-AVR32-04/11
MSTR: Master/Slave Mode
PS: Peripheral Select
PCSDEC: Chip Select Decode
FDIV: Clock Selection
MODFDIS: Mode Fault Detection
LLB: Local Loopback Enable
LLB
CSR0 defines peripheral chip select signals 0 to 3.
CSR1 defines peripheral chip select signals 4 to 7.
CSR2 defines peripheral chip select signals 8 to 11.
CSR3 defines peripheral chip select signals 12 to 14.
31
23
15
–
–
7
SPI Mode Register
30
22
14
–
–
6
–
29
21
13
–
–
5
–
MR
Read/Write
MODFDIS
28
20
12
–
–
4
DLYBCS
FDIV
27
19
11
–
3
PCSDEC
26
18
10
–
2
PCS
PS
25
17
–
9
1
AT32UC3A
MSTR
24
16
–
8
0
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