ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 593

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.8.2.19
Offset:
Register Name:
Access Type:
Reset Value:
• CH_EN: Channel Enable
Set this bit to enable this channel data transfer.
Clear this bit to disable the channel data transfer.
This may be used to start or resume any requested transfer.
This bit is cleared by hardware when the HSB source channel is disabled at end of dma buffer.
• LD_NXT_CH_DESC_EN: Load Next Channel Descriptor Enable
Set this bit to allow automatic next descriptor loading at the end of the channel transfer.
Clear this bit to disable this feature.
If set, the dma channel controller loads the next descriptor when the UDDMAX_STATUS.CH_EN bit is reset due to soft-
ware of hardware event (for example at the end of the current transfer).
• BUFF_CLOSE_IN_EN: Buffer Close Input Enable
Set this bit to automatically closed the current dma transfer at the end of the usb OUT data transfer (received short packet).
Clear this bit to disable this feature.
• DMAEND_EN: End of DMA Buffer Output Enable
Set this bit to properly complete the usb transfer at the end of the dma transfer.
For IN endpoint, it means that a short packet (or a Zero Length Packet) will be sent to the usb line to properly closed the
usb transfer at the end of the dma transfer.
For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.
32058J–AVR32–04/11
BURST_LOCK
_EN
rwu
31
23
15
0
0
–
7
0
USB Device DMA Channel X Control Register (UDDMAX_CONTROL)
DESC_LD_
IRQ_EN
rwu
30
22
14
0
0
–
6
0
EOBUFF_
IRQ_EN
rwu
29
21
13
0
0
–
5
0
0x0318 + (X - 1) . 0x10
UDDMAX_CONTROL, X in [1..6]
Read/Write
0x00000000
EOT_IRQ_EN
rwu
28
20
12
CH_BYTE_LENGTH
CH_BYTE_LENGTH
0
0
–
4
0
rwu
rwu
DMAEND_EN
rwu
27
19
11
0
0
–
3
0
BUFF_CLOSE
_IN_EN
rwu
26
18
10
0
0
–
2
0
LD_NXT_CH_
DESC_EN
rwu
25
17
0
0
9
–
1
0
AT32UC3A
CH_EN
rwu
24
16
0
0
8
–
0
0
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