ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 283

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• CKG: Transmit Clock Gating Selection
• CKI: Transmit Clock Inversion
0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal
input is sampled on Transmit clock rising edge.
1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal
input is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
• CKO: Transmit Clock Output Mode Selection
• CKS: Transmit Clock Selection
32058J-AVR32-04/11
0x3-0x7
CKG
CKO
CKS
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x0
0x1
0x2
0x3
None, continuous clock
Transmit Clock enabled only if TX_FRAME_SYNC Low
Transmit Clock enabled only if TX_FRAME_SYNC High
Reserved
Transmit Clock Output Mode
None
Continuous Transmit Clock
Transmit Clock only during data transfers
Reserved
Selected Transmit Clock
Divided Clock
RX_CLOCK Clock signal
TX_CLOCK Pin
Reserved
Transmit Clock Gating
AT32UC3A
TX_CLOCK pin
Input-only
Output
Output
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