ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 26

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.3
9.3.3.1
9.3.3.2
32058J–AVR32–04/11
Processor States
Debug State
Normal RISC State
Figure 9-5.
The AVR32 processor supports several different execution contexts as shown in
page
Table 9-2.
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a higher priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs executed in this mode are restricted from executing certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accessed. Protected memory areas are also not available. All other operating
modes are privileged and are collectively called System Modes. They have full access to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read out and alter system information for use during application development. This
implies that all system and application registers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.
Bit 15
Priority
1
2
3
4
5
6
N/A
N/A
R
0
26.
T
0
0
-
Mode
Non Maskable Interrupt
Exception
Interrupt 3
Interrupt 2
Interrupt 1
Interrupt 0
Supervisor
Application
0
The Status Register Low Halfword
-
Overview of execution modes, their priorities and privilege levels.
0
-
0
-
0
-
0
-
0
-
Security
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Unprivileged
0
-
L
0
Q
0
V
0
Description
Non Maskable high priority interrupt mode
Execute exceptions
General purpose interrupt mode
General purpose interrupt mode
General purpose interrupt mode
General purpose interrupt mode
Runs supervisor calls
Normal program execution mode
N
0
Z
0
Bit 0
C
0
Bit name
Initial value
Carry
Zero
Sign
Overflow
Saturation
Lock
Reserved
Scratch
Register Remap Enable
AT32UC3A
Table 9-2 on
26