ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 135

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.5.2.2
19.5.2.3
19.5.3
19.6
32058J–AVR32–04/11
Slave and Master assignation
Fixed Priority Arbitration
Round-Robin Arbitration with Last Default Master
Round-Robin Arbitration with Fixed Default Master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to
remove the one latency cycle for the last master that accessed the slave. In fact, at the end of
the current transfer, if no other master request is pending, the slave remains connected to the
last master that performed the access. Other non privileged masters still get one latency cycle if
they want to access the same slave. This technique can be used for masters that mainly perform
single accesses.
This is another biased round-robin algorithm. It allows the Bus Matrix arbiters to remove the one
latency cycle for the fixed default master per slave. At the end of the current access, the slave
remains connected to its fixed default master. Every request attempted by this fixed default mas-
ter will not cause any latency whereas other non privileged masters will still get one latency
cycle. This technique can be used for masters that mainly perform single accesses.
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave by using the fixed priority defined by the user. If two or more master requests are
active at the same time, the master with the highest priority number is serviced first. If two or
more master requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (PRAS and PRBS).
The index number assigned to Bus Matrix slaves and masters are described in Memories
chapter.
AT32UC3A
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