ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 315

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.7.3.5
Figure 26-14. Asynchronous Start Bit Detection
32058J–AVR32–04/11
Manchester Decoder
Manchester
Sampling
encoded
(16 x)
Clock
data
When the MAN field in MR register is set to 1, the Manchester decoder is enabled. The decoder
performs both preamble and start frame delimiter detection. One input line is dedicated to Man-
chester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally indepen-
dent of the emitter side. Use RX_PL in MAN register to configure the length of the preamble
sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addi-
tion, the polarity of the input stream is programmable with RX_MPOL field in MAN register.
Depending on the desired application the preamble pattern matching is to be defined via the
RX_PP field in MAN. See
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder.
So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start
frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame
delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled dur-
ing one quarter of a bit time at zero, a start bit is detected. See
sample pulse rejection mechanism applies.
The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data
at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is
detected, the receiver continues decoding with the same synchronization. If the stream does not
match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next
valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time.
If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming
stream is decoded into NRZ data and passed to USART for processing.
316
USART, the receiver is also able to detect Manchester code violation. A code violation is a lack
of transition in the middle of a bit cell. In this case, MANE flag in CSR register is raised. It is
cleared by writing the Control Register (CR) with the RSTSTA bit at 1. See
316
for an example of Manchester error detection during data phase.
illustrates Manchester pattern mismatch. When incoming data stream is passed to the
Txd
1
2
3
4
Detection
Figure 26-9 on page 312
Start
for available preamble patterns.
Figure 26-14 on page
Figure 26-15 on page
Figure 26-16 on page
AT32UC3A
315.. The
315