ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 282
ATEVK1105
Manufacturer Part Number
ATEVK1105
Description
KIT EVAL FOR AT32UC3A0
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1105.pdf
(28 pages)
Specifications of ATEVK1105
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A0512
Processor Series
AVR
Data Bus Width
32 bit
Interface Type
USART, TWI, USB, SPI, Ethernet
Operating Supply Voltage
3.3 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A0512
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (20Mb)
25.9.5
Name:
Access Type:
Offset:
Reset value:
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period
signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
• STTDLY: Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission
of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.
Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emit-
ted instead of the end of TAG.
• START: Transmit Start Selection
32058J-AVR32-04/11
31
23
15
–
7
0x8 - 0xF
START
Transmit Clock Mode Register
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
CKG
30
22
14
TCMR
Read/Write
0x18
0x00000000
–
6
Transmit Start
Continuous, as soon as a word is written in the THR Register (if Transmit is enabled), and immediately
after the end of transfer of the previous data.
Receive start
Detection of a low level on TX_FRAME_SYNC signal
Detection of a high level on TX_FRAME_SYNC signal
Detection of a falling edge on TX_FRAME_SYNC signal
Detection of a rising edge on TX_FRAME_SYNC signal
Detection of any level change on TX_FRAME_SYNC signal
Detection of any edge on TX_FRAME_SYNC signal
Reserved
CKI
29
21
13
–
5
28
20
12
–
4
PERIOD
STTDLY
CKO
27
19
11
3
26
18
10
2
START
25
17
9
1
AT32UC3A
CKS
24
16
8
0
282
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