ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 25

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3
9.3.1
9.3.2
32058J–AVR32–04/11
Programming Model
Register file configuration
Status register configuration
The AVR32UC register file is shown below.
Figure 9-3.
The Status Register (SR) is split into two halfwords, one upper and one lower, see
page 25
code flags and the R, T and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 9-4.
Application
Bit 31
Bit 31
SP_APP
0
FINTPC
INT0PC
INT1PC
-
SM PC
R12
R11
R10
SR
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
LC
1
0
-
Bit 0
and
0
-
Supe rv isor
Bit 31
Figure 9-5 on page
The AVR32UC Register File
The Status Register High Halfword
SP_SYS
INT0PC
INT1PC
FINTPC
SM PC
0
-
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
DM
0
D
0
INT0
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SM PC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0
-
Bit 0
M2
0
26. The lower word contains the C, Z, N, V and Q condition
M1
INT1
Bit 31
0
SP_SYS
FINTPC
INT0PC
INT1PC
SM PC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
M0
1
Bit 0
E M
1
INT2
Bit 31
I3M
0
SP_SYS
INT0PC
INT1PC
FINTPC
SM PC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
I2M
FE
0
Bit 0
I1M
0
INT3
Bit 31
I0M
SP_SYS
FINTPC
0
INT0PC
INT1PC
SM PC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 16
GM
1
Bit 0
Bit name
Initial value
Global Interrupt Mask
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 2 Mask
Interrupt Level 3 Mask
Mode Bit 0
Mode Bit 1
Mode Bit 2
Reserved
Debug State
Debug State Mask
Reserved
Exception Mask
Exce ption
Bit 31
SP_SYS
AT32UC3A
FINTPC
INT0PC
INT1PC
SM PC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
Figure 9-4 on
NMI
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SM PC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
25