ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 576

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy,
this triggers an EPXINT interrupt if NBUSYBKE = 1.
Note that when the FIFOCON bit is cleared (by setting the FIFOCONC bit) to validate a new bank, this field is updated 2 or
3 clock cycles later to calculate the address of the next bank.
An EPXINT interrupt is triggered if :
- for IN endpoint, NBUSYBKE=1 and all the banks are free.
- for OUT endpoint, NBUSYBKE=1 and all the banks are busy.
• CURRBK: Current Bank
For non-control endpoints, set by hardware to indicate the current bank:
Note that this field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt flag.
• RWALL: Read/Write Allowed
For IN endpoints, set by hardware when the current bank is not full, i.e. the software can write further data into the FIFO.
For OUT endpoints, set by hardware when the current bank is not empty, i.e. the software can read further data from the
FIFO.
Never set if STALLRQ = 1 or in case of error.
Cleared by hardware otherwise.
This bit shall not be used for control endpoints.
• CTRLDIR: Control Direction
Set by hardware after a SETUP packet to indicate the direction of the following packet:
Can not be set or cleared by software.
• CFGOK: Configuration OK Status
This bit is updated when the ALLOC bit is set.
Set by hardware if the endpoint X number of banks (EPBK) and size (EPSIZE) are correct compared to the maximal
allowed number of banks and size for this endpoint and to the maximal FIFO size (i.e. the DPRAM size).
If this bit is cleared by hardware, the user should reprogram the UECFGX register with correct EPBK and EPSIZE values.
• BYCT: Byte Count
Set by the hardware to indicate the byte count of the FIFO.
32058J–AVR32–04/11
0
0
1
1
CTRLDIR
CURRBK
0
1
0
1
0
1
Control Direction
OUT
IN
Current Bank
Bank0
Bank1
Bank2
Reserved
AT32UC3A
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