AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 761

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Version
6175F
Comments (Continued)
TC,
Section 32.5.4 ”External Event/Trigger Conditions”
”EEVT: External Event Selection” page
TWI,
Status and Interrupt register tables.
UDP,
Section 34.4.1 ”USB Device Transceiver”
Section 34.5.1.2 ”USB Bus Transactions”
Section 34.5.1.3 ”USB Transfer Event Definitions”
Section 34.5.2.2 ”Data IN Transaction”
Section 34.5.2 ”Handling Transactions with USB V2.0 Device Peripheral” page
warnings added.
Section 34.5.3 ”Controlling Device States” page
Powered State”
Section 34.6 ”USB Device Port (UDP) User Interface”
Section 34.6.2 ”UDP Global State Register” page
Section 34.6.10 ”UDP Endpoint Control and Status Register” page
Corrections, improvements, additions and deletions throughout section, new source document.
Section
Resume”.
WAKEUP bit shown in interrupt
RMWUPE, RSMINPR, ESR bits removed from
NOTE: pertinent to USB pullup effect on USB Reset added to
Register”.
USART,
output.... RTS output pin.....
Section 30.6.4.1 ”ISO7816 Mode
Section 30.6.3 ”Synchronous and Asynchronous Modes”
Section 30.5.1 ”I/O
Section 30.6.1.3 ”AT91SAM7S512/256/128 Fractional Baud Rate in Asynchronous
“functional mode” changed to “normal mode”
Table 30-3
Figure 30-27 ”IrDA Demodulator Operations” page
Table 30-2, “Baud Rate Example (OVER =
Section 30.6.3.2 ”Asynchronous Receiver”
synchronization mechanism.....”
Section 30.6.3.8 ”Receiver Time-out”
Section 30.7.1 ”USART Control Register”
Section 30.7.6 ”USART Channel Status Register”
register.
WDT, WV changed to WDV in
and 6th and 7th paragraph rewritten on
Table 32-1, “Timer Counter Clock Assignment,” on page 389
”Two-wire Interface (TWI) User Interface” page
Figure 34-2 on page 446
Section 34.5.3.8 ”Sending a Device Remote Wakeup”
Section 30.6.7 ”AT91SAM7S512/256/128/64/321 Modem
and
Table 30-4 on page 312
and
Lines”TXD line information added
Section 34.5.3.2 ”Entering Attached State” page 459
Section 17.2 ”Block Diagram”
updated,
registers:Section 34.6.4 on page 466
Overview”PAR bit usage
list of user options rewritten.
Endpoint use updated.
page 112
412, TIOB chosen as external event signal..... updated in footnote
Di and Fi references corrected in titles.
and
STTTO bit function related to TIMEOUT in US_CSR register.
updated
0)last two lines of table removed.
change to second sentence in fourth paragraph, “For the
Section 34.4.2 ”VBUS Monitoring” page 446
Section 34.6.2 ”UDP Global State
458, Section reworked and
beginning with “To prevent a software deadlock....”
TIMEOUT bit function related to STTTO in US_CR
464,updated.
TIOB defined as external event signal..... updated
updated with endpoint information.
328, Figure modified.
294, UNRE and OVRE bit fields removed from TWI
Manchester Encoder/Decoder feature removed
and in
Section 34.6.12 ”UDP Transceiver Control
replaces title: “Sending an External
has been added.
Mode”change to: The control of DTR
Section 17.3 ”Functional Description”
473, updated
thru
Section 34.6.8 on page
added.
Section 34.5.3.1 ”Not
SAM7S Series [DATASHEET]
450, Section reworked,
Register”.
Mode”USART
added.
6175M–ATARM–26-Oct-12
471.
Change
Request
Ref.
#2470
#2704
#2470
source file
update
3288
#1770
#1552
#2748
#2794 &
rfo review
#2942
#3023
#3002
761