AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 630
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Company:
Part Number:
AT91SAM7S256D-AU
Manufacturer:
ATMEL
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40.7.9.2
40.7.9.3
40.7.10
40.7.10.1
40.7.10.2
None.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge
(rising or falling) of synchro has a Start Delay equal to zero.
None.
If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during
data emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is
lost. This problem does not exist when generating a periodic synchro.
The data need to be delayed for one bit clock period with an external assembly. In the following schematic, TD, TK
and NRST are SAM7S signals, TXD is the delayed data to connect to the device.
The value of CLDIV x 2
equal to 8191⋅
None.
when a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer
in READ or WRITE mode.
None.
Two-wire Interface (TWI)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SSC: Transmitter Limitations in Slave Mode
SSC: Transmitter Limitations in Slave Mode
TWI: Clock Divider
TWI: Software Reset
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
SAM7S Series [DATASHEET]
CKDIV
6175M–ATARM–26-Oct-12
must be less than or
630
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