AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet

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... Battery Backup Power Supply, Providing a Permanent Slow Clock – 12 MHz On-chip Oscillator for Main System Clock and USB Clock – One PLL up to 240 MHz ® ® ARM Thumb Processor ® Acceleration o 2048x2048, Vir AT91 ARM Thumb Microcontrollers AT91SAM9R64 AT91SAM9RL64 Preliminary tual Screen 6289C–ATARM–28-May-09 ...

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... One Four-channel 16-bit PWM Controller (PWMC) • Two Two-wire Interfaces (TWI) – Compatible with Standard Two-wire Serial Memories – One, Two or Three Bytes for Slave Address – Sequential Read/Write Operations AT91SAM9R64/RL64 Preliminary 2 ™ 4.3 Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding 6289C–ATARM–28-May-09 ...

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... Some features are not available for AT91SAM9R64 in the 144-ball BGA package. Separate block diagrams and PIO multiplexing are provided in this document. features and signals of AT91SAM9RL64 that are not available or partially available for AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified. Table 1-1. Feature ...

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... Table 1-1. Feature PWM SPI SSC1 Touchscreen ADC TC TWI USART0 USART1 USART2 USART3 AT91SAM9R64/RL64 Preliminary 4 Unavailable or Partially Available Features and Signals in AT91SAM9R64 Full/Partial Signal Partial PWM2 NPCS2 Partial NPCS3 RF1 RK1 TD1 Full RD1 TK1 TF1 AD3YM Partial GPAD4 GPAD5 TIOA1 ...

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... Block Diagrams Figure 2-1. AT91SAM9R64 Block Diagram 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 5 ...

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... Figure 2-2. AT91SAM9RL64 Block Diagram AT91SAM9R64/RL64 Preliminary 6 6289C–ATARM–28-May-09 ...

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... Wake-Up Input TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select JTAGSEL JTAG Selection 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary gives details on the signal name classified by peripheral. Active Type Level Power Supplies Power Power Power Power Ground Power ...

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... No pullup resistor BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset. D16-D31 not present on AT91SAM9R64 reset NCS2, NCS5 not present on AT91SAM9R64. CFCS1 not present on AT91SAM9R64. 6289C–ATARM–28-May-09 ...

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... CTS0, CTS2, CTS3 not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. TD1 not present on AT91SAM9R64. RD1 not present on AT91SAM9R64. TK1 not present on AT91SAM9R64. RK1 not present on AT91SAM9R64. TF1 not present on AT91SAM9R64. RF1 not present on AT91SAM9R64. 9 ...

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... Not present on AT91SAM9R64. TCLK1 not present on AT91SAM9R64. TIOA1, TIOA2 not present on AT91SAM9R64. TIOB1, TIOB2 not present on AT91SAM9R64. PWM2 not present on AT91SAM9R64. NPCS2, NPCS3 not present on AT91SAM9R64. TWD1 not present on AT91SAM9R64. TWCK1 not present on AT91SAM9R64. GPAD4, GPAD5 not present on AT91SAM9R64. Multiplexed with AD0 ...

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... DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Active Type Level Comments USB High Speed Device Analog Analog Analog Analog ...

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... Package and Pinout The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available in a 217-ball LFBGA package. 4.1 144-ball BGA Package Outline Figure 4-1 Figure 4-1. 144-ball BGA Pinout (Top View) AT91SAM9R64/RL64 Preliminary 12 shows the orientation of the 144-ball BGA package BALL A1 ...

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... Pinout Table 4-1. AT91SAM9R64 Pinout for 144-ball BGA Package Pin Signal Name Pin A1 DFSDM D1 A2 DHSDM D2 A3 XIN D3 A4 XOUT D4 A5 XIN32 D5 A6 XOUT32 D6 A7 TDO D7 A8 PA[31 PA[22] D9 A10 PA[16] D10 A11 PA[14] D11 A12 PA[11] D12 B1 DFSDP E1 B2 ...

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... LFBGA Package Outline Figure 4-2 Figure 4-2. 217-ball LFBGA Pinout (Top View) AT91SAM9R64/RL64 Preliminary 14 shows the orientation of the 217-ball LFBGA package BALL A1 6289C–ATARM–28-May-09 ...

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... PA[16] C14 PA[11] C15 PD[18] C16 PA[7] C17 PA[6] D1 PLLRCA D2 NWR1/NBS1/CFIOR D3 GND D4 GND Note: 1. Shaded cells define the pins powered by VDDIOM. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Pin Signal Name Pin D5 SHDN J14 D6 JTAGSEL J15 D7 NTRST J16 D8 BMS J17 D9 TDO K1 D10 PA[30] ...

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... Power Considerations 5.1 Power Supplies The AT91SAM9R64/RL64 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). • ...

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... Slow Clock Mode. The PIO lines are supplied through VDDIOP and the speed of the signal that can be driven on them can reach 50 MHz with 50 pF load. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Example of PLL and USB Power Supplies VIN VOUT CE 10µ ...

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... PIO Controllers All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product datasheet for more details. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “ ...

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... Matrix Masters The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 masters, which means that each master can perform an access concurrently with others available slave. Each master has its own decoder, which is defined specifically for each master. In order to sim- plify the addressing, all the masters have the same decodings. ...

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... Table 7-1. Master 3 Master 4 Master 5 7.3 Matrix Slaves The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 7.4 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “ ...

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... Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary USART0 Transmit Channel SSC1 Transmit Channel SSC0 Transmit Channel DBGU Receive Channel AC97 Receive Channel ...

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... Memories Figure 8-1. AT91SAM9R64/RL64 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes ...

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... Notes: 8.1.1.1 Internal SRAM The AT91SAM9R64/RL64 product embeds a total of 64Kbyte high-speed SRAM split in 4 blocks of 16KBytes. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. ...

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... RB2 SRAM C 0x0030 8000 RB1 (AHB) 0x0030 C000 RB0 Note: 1. Configuration after reset. AT91SAM9R64/RL64 Preliminary 24 0 16K Bytes 32K Bytes illustrates different configurations and the related 16-Kbyte blocks (RB0 to RB3) Configuration examples and related 16-Kbyte block assignments I = 16K I =32K ...

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... Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The AT91SAM9R64/RL64 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect ...

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... Switch the main clock to the new value 8.2 External Memories The AT91SAM9R64/RL64 features one External Bus Interface to offer interface to a wide range of external memories and to any parallel peripheral. 8.2.1 External Bus Interface • Integrates three External Memory Controllers: – ...

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... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary detected erroneous pages 27 ...

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... However, all the registers of System Controller are mapped on the top of the address space. This allows addressing all the registers of the System Controller from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of +/- 4kbytes. AT91SAM9R64/RL64 Preliminary 28 Figure 8-1, the System Controller’s peripherals are all mapped within the highest ...

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... XOUT32 OSC XIN 12MHz MAIN OSC XOUT UPLL PLLRCA PLLA periph_nreset periph_nreset periph_clk[2..4] PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD21 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary System Controller VDDCORE Powered irq0-irq2 Advanced fiq Interrupt Controller int MCK Debug dbgu_irq Unit dbgu_txd dbgu_rxd MCK Periodic debug ...

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... One 80 to 240 MHz programmable PLL, providing the PLL Clock (PLLCK). This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, the only limitation being the lowest input frequency shall be higher or equal to 1 MHz. AT91SAM9R64/RL64 Preliminary 30 6289C–ATARM–28-May-09 ...

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... Slow Clock Selection 9.6.1 Description The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external slow clock on XIN32. Configuration is located in the slow clock control register (SCKCR) located at address 0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is present ...

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... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9R64/RL64 Power Management Controller Block Diagram Master Clock Controller SLCK MAINCK PLLCK 9 ...

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... Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary enabled processor Generator 33 ...

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... Peripheral Mapping As shown in space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space. AT91SAM9R64/RL64 Preliminary 34 the ARM Processor’s ICE Interface Figure 8-1, the Peripherals are mapped in the upper 256M bytes of the address ...

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... LCDC 24 AC97 25- AIC Note: 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary defines the Peripheral Identifiers of the AT91SAM9R64/RL64. A peripheral iden- Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D USART 0 USART 1 USART 2 USART 3 ...

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... Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.4 Peripherals Signals Multiplexing on I/O Lines The AT91SAM9R64/RL64 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which mul- tiplexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...

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... PA23 TWD0 PA24 TWCK0 PA25 MISO PA26 MOSI PA27 SPCK PA28 NPCS0 PA29 RTS2 PA30 CTS2 PA31 NWAIT 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Reset Power Peripheral B State Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP TCLK0 I/O VDDIOP TIOA0 I/O VDDIOP TIOB0 ...

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... PB22 D22 PB23 D23 PB24 D24 PB25 D25 PB26 D26 PB27 D27 PB28 D28 PB29 D29 PB30 D30 PB31 D31 AT91SAM9R64/RL64 Preliminary 38 Reset Power Peripheral B State Supply I/O VDDIOP I/O VDDIOP A21 VDDIOM A22 VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM ...

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... PC23 LCDD15 PC24 LCDD16 PC25 LCDD17 PC26 LCDD18 PC27 LCDD19 PC28 LCDD20 PC29 LCDD21 PC30 LCDD22 PC31 LCDD23 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Reset Power Peripheral B State Supply I/O VDDIOP LCDPWR I/O VDDIOP PWM0 I/O VDDIOP PWM1 I/O VDDIOP I/O VDDIOP ...

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... NPCS3 PD14 DSR0 PWM0 PD15 DTR0 PWM1 PD16 DCD0 PWM2 PD17 RI0 PD18 PWM3 PD19 PCK0 PD20 PCK1 PD21 TCLK2 AT91SAM9R64/RL64 Preliminary 40 Reset Power Comments State Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDANA ...

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... AT91SAM9R64 PIO Multiplexing Note: In Table 10-6, Table 10-7, Table 10-8 AT91SAM9R64. 10.4.2.1 AT91SAM9R64 PIO Controller A Multiplexing Table 10-6. AT91SAM9R64 Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 MC_DA0 PA1 MC_CDA PA2 MC_CK PA3 MC_DA1 PA4 MC_DA2 PA5 MC_DA3 PA6 ...

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... AT91SAM9R64 PIO Controller B Multiplexing Table 10-7. AT91SAM9R64 Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 TXD3 PB1 RXD3 PB2 A21/NANDALE PB3 A22/NANDCLE PB4 NANDOE PB5 NANDWE PB6 NCS3/NANDCS PB7 NCS4/CFCS0 PB8 CFCE1 PB9 CFCE2 PB10 A25/CFRNW PB11 A18 PB12 ...

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... AT91SAM9R64 PIO Controller C Multiplexing Table 10-8. AT91SAM9R64 Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 TF0 PC1 TK0 PC2- NA PC31 10.4.2.4 AT91SAM9R64 PIO Controller D Multiplexing Table 10-9. AT91SAM9R64 Multiplexing on PIO Controller D PIO Controller D I/O Line Peripheral A Peripheral B PD0- NA PD17 ...

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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first AT91SAM9R64/RL64 Preliminary 44 peripherals Sensors and data per chip select ...

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... Variable sampling rate AC97 Codec Interface (48KHz and below) 11.6 Timer Counter (TC) • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 2 S, TDM Buses, Magnetic Card Reader, etc.) 45 ...

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... USB V2.0 high-speed compliant, 480 MBits per second • Embedded USB V2.0 UTMI+ high-speed transceiver • Embedded 4K-byte dual-port RAM for endpoints • Embedded 6 channels DMA controller • Suspend/Resume logic • banks for isochronous and bulk endpoints • Seven endpoints: AT91SAM9R64/RL64 Preliminary 46 6289C–ATARM–28-May-09 ...

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... Multiple trigger sources – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary enabled channels 47 ...

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... AT91SAM9R64/RL64 Preliminary 48 6289C–ATARM–28-May-09 ...

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... The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S • a Memory Management Unit (MMU) • separate instruction and data AMBA • separate instruction and data TCM interfaces 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary ™ integer core ® AHB bus interfaces ™ ...

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... Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 12.3.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC AT91SAM9R64/RL64 Preliminary 50 ARM926EJ-S Coprocessor Interface Droute ...

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... User mode is the usual ARM program execution state used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 51 ...

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... R13 R14 PC CPSR The ARM state register set contains 16 directly-accessible registers r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose AT91SAM9R64/RL64 Preliminary 52 shows all the registers in all modes. ™ ARM9TDMI Modes and Registers Layout Supervisor ...

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... The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 53 ...

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... More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen excep- tions according to the following priority order: • Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) AT91SAM9R64/RL64 Preliminary Reserved Jazelle state bit ...

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... ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary into LR (current PC(r15 depending on the exception). (current depending on the exception) that causes the program to resume from the correct place on return. 55 ...

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... B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP AT91SAM9R64/RL64 Preliminary 56 gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply ...

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... Table 5 shows the Thumb instruction set. Table 12-4. Mnemonic MOV ADD SUB CMP TST AND 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary New ARM Instruction Mnemonic List Operation Branch and exchange to Java (1) Branch, Link and exchange Signed Multiply Accumulate bit Signed Multiply Accumulate ...

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... Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 12-5. Register AT91SAM9R64/RL64 Preliminary 58 Thumb Instruction Mnemonic List (Continued) Operation Logical Exclusive OR Logical Shift Left Arithmetic Shift Right ...

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... Table 12-5. Register Notes: 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary CP15 Registers Name 8 TLB operations (2) 9 cache lockdown 9 TCM region 10 TLB lockdown 11 Reserved 12 Reserved (1) 13 FCSE PID (1) 13 Context ID 14 Reserved 15 Test configuration 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field ...

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... L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. AT91SAM9R64/RL64 Preliminary 60 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 ...

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... Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Mapping Details Mapping Size Access Permission By ...

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... The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. AT91SAM9R64/RL64 Preliminary 62 6289C–ATARM–28-May-09 ...

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... DCache can be enabled or disabled by writing either bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 63 ...

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... TCM region register (register 9) in CP15 maps TCMs and enables them. The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable code to be loaded into the ITCM, for SWI and emulated instruction handlers, and for accesses to PC-relative literal pools. AT91SAM9R64/RL64 Preliminary 64 6289C–ATARM–28-May-09 ...

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... The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 65 ...

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... The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. AT91SAM9R64/RL64 Preliminary 66 Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT that has missed in DCache) • ...

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... AT91SAM9R64/RL64 Debug and Test 13.1 Description The AT91SAM9R64/RL64 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel ...

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... Block Diagram Figure 13-1. Debug and Test Block Diagram Boundary Port ARM9EJ-S ARM926EJ-S PDC TAP: Test Access Port AT91SAM9R64/RL64 Preliminary 68 ICE/JTAG TAP Reset and Test ICE-RT DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR TST DTXD DRXD 6289C–ATARM–28-May-09 ...

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... In this example, the “board in test” is designed using a number of JTAG- compliant devices. These devices can be connected to form a single scan chain. Figure 13-3. Application Test Environment Example 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary shows a complete debug environment example. The ICE/JTAG inter- ICE/JTAG Interface ...

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... ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document: ARM9EJ-S Technical Reference Manual (DDI 0222A). 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Debug and Test Pin List Function Reset/Test Test Reset Signal ...

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... Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9R64/RL64 Debug Unit Chip ID value is 0x0196 07A0 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 13.5.5 IEEE 1149 ...

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... MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_003F. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B20. • VERSION[31:28]: Product Version Number Set to 0x0. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary PART NUMBER 13 12 ...

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... AT91SAM9R64/RL64 Boot Program 14.1 Description The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. Then the SD Card Boot program is executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card ...

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... UTMI PLL is enabled to generate a 480MHz clock necessary to use the USB High Speed Device. 5. PLL setup: PLL is initialized to generate a 96 MHz clock. Note: 6. MCK is configured to generate a 48MHz clock (PLL/2). 7. Initialization of the DBGU serial port (115200 bauds Enable the user reset AT91SAM9R64/RL64 Preliminary 74 Yes Download from SD Card (MCI) Yes Download from ...

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... ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his own vector (see 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Internal ROM REMAP Internal ...

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... The size of the image to load into SRAM is contained in the location of the sixth ARM vector. Thus the user must replace this vector by the correct vector for his application. 14.4.3 DataFlash Boot Sequence The DataFlash boot program performs device initialization followed by the download procedure. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary ...

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... AT45DB161 AT45DB321 AT45DB642 The DataFlash has a Status Register that determines all the parameters required to access the device. The DataFlash boot is configured to be compatible with the future design of the DataFlash. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary DataFlash Device Density 1 Mbit 2 Mbits 4 Mbits 8 Mbits ...

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... NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory valid application is found, this application is loaded into internal SRAM and executed by branch- 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Start Send status command No Is status OK ? Yes ...

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... Address: Address in hexadecimal – Output: ‘>’. Note: • Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary loop waiting for different commands as in Commands Available through the SAM-BA Boot Action Argument(s) write a byte ...

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... CRC16 Figure 14-7 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary : Number of bytes in hexadecimal to receive NbOfBytes to 01) shows a transmission using this protocol. ...

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... USB Specification. Table 14-3. Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION GET_STATUS SET_FEATURE CLEAR_FEATURE 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Handled Standard Requests Definition Returns the current device configuration value ...

Page 82

... For the DataFlash driven by the SPCK signal at 8 MHz, the time to download 60 K bytes is reduced to 200 ms. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. ...

Page 83

... MCI MCI SPI SPI SPI SPI PIO Controller B PIO Controller B PIO Controller B Address Bus Address Bus DBGU DBGU 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Pins Driven during Boot Program Execution Pin MCDA0 MCCDA MCCK MCDA1 MCDA2 MCDA3 MISO MOSI SPCK NPCS0 NAND OE ...

Page 84

... AT91SAM9R64/RL64 Preliminary 84 6289C–ATARM–28-May-09 ...

Page 85

... The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 15.2 Block Diagram Figure 15-1. Reset Controller Block Diagram Main Supply POR Backup Supply POR NRST WDRPROC wd_fault 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Reset Controller Startup Counter Reset State Manager user_reset NRST Manager nrst_out exter_nreset SLCK ...

Page 86

... User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN RSTC_MR disables the User Reset trigger. AT91SAM9R64/RL64 Preliminary 86 Figure 15-2 shows the block diagram of the NRST Manager. ...

Page 87

... The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 15-3. BMS Sampling SLCK Core Supply POR output BMS Signal proc_nreset 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs XXX BMS sampling delay = 3 cycles ...

Page 88

... MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) AT91SAM9R64/RL64 Preliminary 88 shows how the General Reset affects the reset signals. Startup Time Processor Startup = 3 cycles XXX EXTERNAL RESET LENGTH = 2 cycles Any Freq. 0x0 = General Reset ...

Page 89

... Main Supply POR. Figure 15-5. Wake-up State SLCK MCK Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Resynch. Processor Startup 2 cycles = 3 cycles XXX EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) Any Freq. 0x1 = WakeUp Reset XXX 89 ...

Page 90

... NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 15-6. User Reset State SLCK Any MCK Freq. NRST Resynch. 2 cycles proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) AT91SAM9R64/RL64 Preliminary Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH Processor Startup = 3 cycles 0x4 = User Reset 6289C– ...

Page 91

... As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog- ress) is set in the Status Register (RSTC_SR cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 91 ...

Page 92

... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. AT91SAM9R64/RL64 Preliminary 92 Any Resynch. ...

Page 93

... A User Reset cannot be entered. 15.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Any Freq. Processor Startup = 3 cycles Any XXX proc_nreset signal ...

Page 94

... URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 15-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM9R64/RL64 Preliminary 94 read RSTC_SR 2 cycle resynchronization 6289C–ATARM–28-May-09 Figure ...

Page 95

... Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read/Write Back-up Reset ...

Page 96

... PERRST: Peripheral Reset effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9R64/RL64 Preliminary KEY – ...

Page 97

... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – ...

Page 98

... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9R64/RL64 Preliminary ...

Page 99

... Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary set 0 RTT_SR RTTINC ...

Page 100

... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM9R64/RL64 Preliminary 100 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...

Page 101

... Register Mapping Table 16-1. Real-time Timer Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Name Access RTT_MR Read/Write RTT_AR Read/Write RTT_VR Read-only RTT_SR Read-only Reset Value 0x0000_8000 0xFFFF_FFFF ...

Page 102

... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM9R64/RL64 Preliminary 102 – ...

Page 103

... Defines the alarm value (ALMV+1) compared with the Real-time Timer. 16.4.4 Real-time Timer Value Register Register Name: RTT_VR Access Type: Read-only • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary ALMV ALMV ALMV ALMV 29 ...

Page 104

... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM9R64/RL64 Preliminary 104 – ...

Page 105

... Block Diagram Figure 17-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR set 0 PIT_SR PITS reset 0 ...

Page 106

... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. AT91SAM9R64/RL64 Preliminary 106 Figure 17-2 illustrates 6289C– ...

Page 107

... Figure 17-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 107 ...

Page 108

... Table 17-1. Periodic Interval Timer (PIT) Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM9R64/RL64 Preliminary 108 Name Access PIT_MR Read/Write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset Value ...

Page 109

... PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – – – ...

Page 110

... PIT_PIIR Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. AT91SAM9R64/RL64 Preliminary 110 PICNT CPIV CPIV ...

Page 111

... Block Diagram Figure 18-1. Watchdog Timer Block Diagram write WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD ...

Page 112

... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM9R64/RL64 Preliminary 112 6289C–ATARM–28-May-09 ...

Page 113

... Figure 18-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9R64/RL64 Preliminary 113 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6289C–ATARM–28-May-09 ...

Page 114

... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9R64/RL64 Preliminary 114 Name WDT_CR WDT_MR WDT_SR KEY – – ...

Page 115

... The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. AT91SAM9R64/RL64 Preliminary 115 WDDBGHLT 21 ...

Page 116

... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM9R64/RL64 Preliminary 116 – ...

Page 117

... Shutdown output 19.4 Product Dependencies 19.4.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Con- troller has no effect on the behavior of the Shutdown Controller. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary read SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset ...

Page 118

... SHDW_SR. When using the RTC alarm to wake up the system, the user must ensure that the RTC alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails fail. AT91SAM9R64/RL64 Preliminary 118 6289C–ATARM–28-May-09 ...

Page 119

... Shutdown Controller (SHDWC) User Interface Table 19-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0003 0x0000_0000 119 ...

Page 120

... SHDW: Shutdown Command effect KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9R64/RL64 Preliminary 120 KEY – – – – ...

Page 121

... The RTT Alarm signal forces the de-assertion of the SHDN pin. • RTCWKEN: Real-time Clock Wake-up Enable 0 = The RTC Alarm signal has no effect on the Shutdown Controller The RTC Alarm signal forces the de-assertion of the SHDN pin. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – ...

Page 122

... At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. • RTCWK: Real-time Clock Wake- wake-up alarm from the RTC occurred since the last read of SHDW_SR least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. AT91SAM9R64/RL64 Preliminary 122 – ...

Page 123

... Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32768 Divider Time Bus Interface Entry Control ...

Page 124

... This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: 1. Century (check range 19 - 20) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check BCD range 01 - 12, check validity regarding “date”) AT91SAM9R64/RL64 Preliminary 124 6289C–ATARM–28-May-09 ...

Page 125

... Note: 1. Values in the Version Register vary with the version of the IP block implementation. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be pro- grammed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked ...

Page 126

... AT91SAM9R64/RL64 Preliminary 126 6289C–ATARM–28-May-09 ...

Page 127

... CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Week change (every Monday at time 00:00:00 Month change (every 01 of each month at time 00:00:00 Year change (every January 1 at time 00:00:00). 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – – ...

Page 128

... RTC_MR Access Type: Read/Write 31 30 – – – – – – – – • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected 12-hour mode is selected. All non-significant bits read zero. AT91SAM9R64/RL64 Preliminary 128 – – – – – – – – – – ...

Page 129

... HOUR: Current Hour The range that can be set (BCD) in 12-hour mode (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode AM PM. All non-significant bits read zero. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – – – 21 ...

Page 130

... The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Date The range that can be set (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. AT91SAM9R64/RL64 Preliminary 130 ...

Page 131

... This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled The hour-matching alarm is enabled. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – – – ...

Page 132

... MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled The date-matching alarm is enabled. AT91SAM9R64/RL64 Preliminary 132 – ...

Page 133

... No calendar event has occurred since the last clear least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – ...

Page 134

... No effect Clears corresponding status flag in the Status Register (RTC_SR). • TIMCLR: Time Clear effect Clears corresponding status flag in the Status Register (RTC_SR). • CALCLR: Calendar Clear effect Clears corresponding status flag in the Status Register (RTC_SR). AT91SAM9R64/RL64 Preliminary 134 – – – ...

Page 135

... No effect The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable effect The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable effect. • The selected calendar event interrupt is enabled. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – – – – ...

Page 136

... SECDIS: Second Event Interrupt Disable effect The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable effect The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable effect The selected calendar event interrupt is disabled. AT91SAM9R64/RL64 Preliminary 136 – – – 21 ...

Page 137

... TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled The selected calendar event interrupt is enabled. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – – – ...

Page 138

... No invalid data has been detected in RTC_TIMALR (Time Alarm Register RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non valid Calendar Alarm invalid data has been detected in RTC_CALALR (Calendar Alarm Register RTC_CALALR has contained invalid data since it was last programmed. AT91SAM9R64/RL64 Preliminary 138 – ...

Page 139

... Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus bits six chip select lines (NCS[5:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 139 ...

Page 140

... Block Diagram 21.2.1 External Bus Interface 0 Figure 21-1 Figure 21-1. Organization of the External Bus Interface 0 Bus Matrix AHB Address Decoders AT91SAM9R64/RL64 Preliminary 140 shows the organization of the External Bus Interface 0. External Bus Interface 0 SDRAM Controller MUX Static Logic Memory Controller ...

Page 141

... EBI_RAS - EBI_CAS Row and Column Signal EBI_NWR0 - EBI_NWR3 Write Signals EBI_NBS0 - EBI_NBS3 Byte Mask Signals EBI_SDA10 SDRAM Address 10 Line 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary EBI SMC EBI for CompactFlash Support EBI for NAND Flash Support SDRAM Controller Type Active Level I/O ...

Page 142

... EBI_A1/NBS2/NWR2 EBI_A[11:2] EBI_SDA10 EBI_A12 EBI_A[14:13] EBI_A[22:15] EBI_A[25:23] EBI_D[31:0] 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary details the connections between the two Memory Controllers and the EBI Pins and Memory Controllers I/O Lines Connections (1) EBIx Pins SDRAMC I/O Lines NBS1 Not Supported Not Supported ...

Page 143

... NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. 4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word. 5. BEx: Byte x Enable (x = 0,1 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary details the connections to be applied between the EBI pins and the Pins of the Interfaced Device 2 x 8-bit ...

Page 144

... A22/NANDCLE A23 - A24 A25 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 NANDOE NANDWE NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW CFCE1 CFCE2 SDCK 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Pins of the Interfaced Device CompactFlash SDRAM (EBI only) SDRAMC D15 D16 - D31 – DQM0 A0 DQM2 A1 A[0:8] A[2:10] A9 – ...

Page 145

... Pxx Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot. 2. Any PIO line. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Pins of the Interfaced Device CompactFlash SDRAM (EBI only) SDRAMC CKE – ...

Page 146

... It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: • the Static Memory Controller (SMC) • the SDRAM Controller (SDRAMC) 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary shows an example of connections between the EBI and external devices SDRAM D0-D7 ...

Page 147

... FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup- ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 147 ...

Page 148

... NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 148. Offset 0x00E0 0000 Offset 0x00C0 0000 ...

Page 149

... NCS4 (and/or NCS5) chip select to the appropriate values. For details on these signal waveforms, please refer to the section: Setup and Hold Cycles of the Static Memory Controller section. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary CFCE1 DBW Comment NBS0 ...

Page 150

... EBI_CSA Register in the Chip Configuration User Interface is set. These pins must not be used to drive any other memory devices. The EBI pins in responding CompactFlash interface is enabled (EBI_CS4A = 1 and/or EBI_CS5A = 1). Table 21-8. Dedicated CompactFlash Interface Multiplexing Pins CS4A = 1 NCS4/CFCS0 CFCS0 NCS5/CFCS1 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary A23 A22 NRD_NOE NWR0_NWE CFOE ...

Page 151

... The CompactFlash _WAIT sig- nal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the Static Memory Controller Section. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Access to CompactFlash Device CompactFlash Signals CFOE ...

Page 152

... NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. See Figure Signal Multiplexing on EBI Pins” on page 153 forms, refer to the Static Memory Controller section. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary CompactFlash Connector D[15:0] DIR /OE ...

Page 153

... PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. Figure 21-7. NAND Flash Application Example EBI Note: 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary NAND Flash Logic NCSx NRD D[7:0] A[22:21] ...

Page 154

... Select Assignment Register located in the bus matrix memory space. • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width programmed to 16 bits. The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller (SDRAMC)”. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary ...

Page 155

... The Data Bus Width programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller (SDRAMC)”. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary ...

Page 156

... PIOs must be programmed in peripheral mode in the PIO controller. • Configure a PIO line as an input to manage the Ready/Busy signal. • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. AT91SAM9R64/RL64 Preliminary 156 U1 U1 ...

Page 157

... D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.7.4.2 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode register of the Static Memory Controller. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary CLE 17 ALE ...

Page 158

... The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. AT91SAM9R64/RL64 Preliminary 158 U1 U1 ...

Page 159

... A10 3V3 A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 B1 B6 1B4 1A4 CF_D11 C2 C5 ...

Page 160

... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9R64/RL64 Preliminary 160 6289C–ATARM–28-May-09 ...

Page 161

... A10 3V3 A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 B1 B6 1B4 1A4 CF_D11 C2 C5 ...

Page 162

... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9R64/RL64 Preliminary 162 6289C–ATARM–28-May-09 ...

Page 163

... NBS1 A1 NWR2 NBS2 NWR3 NBS3 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Related Function Byte-write or byte-select access, see 8-bit or 16-/32-bit data bus, see “Data Bus Width” on page 165 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 165 8-/16-bit or 32-bit data bus, see “ ...

Page 164

... The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. AT91SAM9R64/RL64 Preliminary 164 128K x 8 ...

Page 165

... Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary NCS2 NCS1 NCS0 shows how to connect a 512K x 8-bit memory on NCS2 ...

Page 166

... Figure 22-3. Memory Connection for an 8-bit Data Bus Figure 22-4. Memory Connection for a 16-bit Data Bus Figure 22-5. Memory Connection for a 32-bit Data Bus SMC AT91SAM9R64/RL64 Preliminary 166 D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[15:0] A[19:2] A1 NBS0 SMC NBS1 NWE NRD ...

Page 167

... Byte Select Access is used to connect two 16-bit devices. Figure 22-7 mode, on NCS3 (BAT = Byte Select Access). 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 22-6. shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access 167 ...

Page 168

... For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. AT91SAM9R64/RL64 Preliminary 168 D[7:0] D[15:8] ...

Page 169

... NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary D[15:0] D[31:16] A[25:2] ...

Page 170

... NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. AT91SAM9R64/RL64 Preliminary 170 Figure 22-8. NRD_SETUP NRD_PULSE ...

Page 171

... NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 22.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 22-9). 171 ...

Page 172

... NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. AT91SAM9R64/RL64 Preliminary 172 NRD_PULSE NRD_PULSE ...

Page 173

... Figure 22-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary t PACC Data Sampling shows the typical read cycle of an LCD module. The read data is valid t t PACC Data Sampling after PACC ...

Page 174

... NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 22-12. Write Cycle MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NCS_WR_SETUP AT91SAM9R64/RL64 Preliminary 174 NWE_SETUP NWE_PULSE NCS_WR_PULSE NWE_CYCLE Figure 22-12. The write cycle NWE_HOLD NCS_WR_HOLD 6289C–ATARM–28-May-09 ...

Page 175

... NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 22.8.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE Figure 22-13). How- NWE_PULSE NCS_WR_PULSE ...

Page 176

... NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. AT91SAM9R64/RL64 Preliminary 176 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is shows the waveforms of a write operation with WRITE_MODE set to 0. The data is 6289C– ...

Page 177

... Number of Bits setup [5:0] 6 pulse [6:0] 7 cycle [8:0] 9 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary shows how the timing parameters are coded and their permitted range. Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] Permitted Range Coded Value Effective Value 0 ≤ ...

Page 178

... During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..5], NRD lines are all set to 1. Figure 22-16 Select 2. AT91SAM9R64/RL64 Preliminary 178 gives the default value of timing parameters at reset. Reset Values of Timing Parameters Reset Value ...

Page 179

... If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary NRD_CYCLE Read to Write Wait State (Figure 22-17) ...

Page 180

... Figure 22-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD D[31:0] AT91SAM9R64/RL64 Preliminary 180 no hold write cycle Early Read wait state no hold write cycle Early Read ...

Page 181

... SMC_MODE, even if no change was made on the mode parameters. 22.9.3.2 Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary MCK no hold NRD write cycle Early Read (WRITE_MODE = 1) ...

Page 182

... SMC accesses. This wait cycle is referred read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See AT91SAM9R64/RL64 Preliminary 182 Figure 22-16 on page 179. 6289C–ATARM–28-May-09 ...

Page 183

... Figure 22-20 assuming a data float period of 2 cycles (TDF_CYCLES = 2). ation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary ) for each external memory device is programmed in the DF will not slow down the execution of a program from internal ...

Page 184

... Figure 22-21. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS D[31:0] AT91SAM9R64/RL64 Preliminary 184 tpacc TDF = 2 clock cycles NRD controlled read operation tpacc TDF = 3 clock cycles NCS controlled read operation 6289C–ATARM–28-May-09 ...

Page 185

... TDF optimization. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary shows a read access controlled by NRD, followed by a write access controlled by NRD_HOLD= 4 TDF_CYCLES = 6 ...

Page 186

... NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 cycle TDF_CYCLES = 4 AT91SAM9R64/RL64 Preliminary 186 read1 hold = 1 TDF_CYCLES = 6 5 TDF WAIT STATES Chip Select Wait State read1 hold = 1 TDF_CYCLES = 4 2 TDF WAIT STATES Read to Write Chip Select ...

Page 187

... SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary read1 hold = 1 TDF_CYCLES = 5 read1 cycle Read to Write Wait State (“ ...

Page 188

... The assertion of the NWAIT signal outside the expected period is ignored as illustrated in 22-27. Figure 22-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal AT91SAM9R64/RL64 Preliminary 188 FROZEN STATE Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 1 ...

Page 189

... Figure 22-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary FROZEN STATE Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 ...

Page 190

... Figure 22-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 Figure 22-28 and Figure 22-29 ...

Page 191

... Figure 22-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 Wait STATE ...

Page 192

... NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 22-30. NWAIT Latency MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWAIT intenally synchronized NWAIT signal 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary minimal pulse length NWAIT latency 2 cycle resynchronization Read cycle EXNW_MODE = READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 WAIT STATE ...

Page 193

... NRD_SETUP NRD_PULSE NCS_RD_SETUP NCS_RD_PULSE NRD_CYCLE 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary illustrates the read and write operations in slow clock mode. They are valid on all Table 22-6 indicates the value of read and write parameters in slow clock mode Read and Write Timing Parameters in Slow Clock Mode ...

Page 194

... A0,A1 NWE NCS SLOW CLOCK MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary illustrates the recommended procedure to properly switch from one mode to the NWE_CYCLE = 3 SLOW CLOCK MODE WRITE ...

Page 195

... Figure 22-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK MODE WRITE 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 1 1 IDLE STATE NORMAL MODE WRITE Reload Configuration Wait State 195 ...

Page 196

... User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary ) as shown in sa Page Address and Data Address within a Page ...

Page 197

... AT91SAM9R64/RL64 Preliminary Programming of Read Timings in Page Mode Value Definition ‘ ...

Page 198

... Figure 22-35. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Page address A1 D1 NRD_PULSE NCS_RD_PULSE NRD_PULSE 198 ...

Page 199

... SMC Pulse Register 0x10 x CS_number + 0x08 SMC Cycle Register 0x10 x CS_number + 0x0C SMC Mode Register 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 22-9. For each chip select, a set of 4 registers is used to pro- Table 22-9, “CS_number” denotes the chip select number. Name ...

Page 200

... The NRD signal setup length is defined in clock cycles as: NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles • NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary NCS_RD_SETUP 21 ...