AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 299

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 29-7. Master Write with One Byte Internal Address and Multiple Data Bytes
29.6.4
TXCOMP
TXRDY
TWD
Write THR (Data n)
Master Receiver Mode
S
DADR
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
Figure 29-8. Master Read with One Data Byte
W
A
IADR(7:0)
TXCOMP
RXRDY
TWD
Figure
A
S
Write START &
29-9. For Internal Address usage see
DATA n
Write THR (Data n+1)
STOP Bit
DADR
A
R
Figure
A
Write THR (Data n+x)
DATA n+5
Last data sent
29-8. When a multiple data byte read is
SAM7S Series [DATASHEET]
DATA
A
Read RHR
Section
(ACK received and TXRDY = 1)
N
DATA n+x
6175M–ATARM–26-Oct-12
STOP sent automaticaly
Figure
P
29.6.5.
29-9. When the
A
P
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