AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 152

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

22.3
22.3.1
22.3.2
22.3.3
Functional Description
The PDC channels user interface enables the user to configure and control the data transfers for each channel.
The user interface of a PDC channel is integrated into the user interface of the peripheral (offset 0x100), which it is
related to.
Per peripheral, it contains four 32-bit Pointer Registers (RPR, RNPR, TPR, and TNPR) and four 16-bit Counter
Registers (RCR, RNCR, TCR, and TNCR).
The size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is pos-
sible, at any moment, to read the number of transfers left for each channel.
The memory base address is configured in a 32-bit memory pointer by defining the location of the first address to
access in the memory. It is possible, at any moment, to read the location in memory of the next transfer and the
number of remaining transfers. The PDC has dedicated status registers which indicate if the transfer is enabled or
disabled for each channel. The status for each channel is located in the peripheral status register. Transfers can be
enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC Transfer Control Register. These
control bits enable reading the pointer and counter registers safely without any risk of their changing between both
reads.
The PDC sends status flags to the peripheral visible in its status-register (ENDRX, ENDTX, RXBUFF, and
TXBUFE).
ENDRX flag is set when the PERIPH_RCR register reaches zero.
RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
ENDTX flag is set when the PERIPH_TCR register reaches zero.
TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
These status flags are described in the peripheral status register.
Each peripheral is connected to the PDC by a receiver data channel and a transmitter data channel. Each channel
has an internal 32-bit memory pointer. Each memory pointer points to a location anywhere in the memory space
(on-chip memory or external bus interface memory).
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4,
respectively for peripheral transfers.
If a memory pointer is reprogrammed while the PDC is in operation, the transfer address is changed, and the PDC
performs transfers using the new address.
There is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred
by its associated channel. These counters are decremented after each data transfer. When the counter reaches
zero, the transfer is complete and the PDC stops transferring data.
If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral
end flag.
If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts
transfers from the new value.
Configuration
Memory Pointers
Transfer Counters
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
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