AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 163
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
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23.6
23.6.1
23.6.2
23.6.3
Product Dependencies
The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on
the features of the PIO controller used in the product, the pins must be programmed in accordance with their
assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the
input path.
The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the
Advanced Interrupt Controller behavior.
The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor
while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without
asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.
The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0
cannot be used.
The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system
peripheral interrupt lines, such as the System Timer, the Real Time Clock, the Power Management Controller and
the Memory Controller. When a system interrupt occurs, the service routine must first distinguish the cause of the
interrupt. This is performed by reading successively the status registers of the above mentioned system
peripherals.
The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to
external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller.
The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO
Controller interrupt lines are connected to the Interrupt Sources 2 to 31.
The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the
bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional opera-
tions and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.
I/O Lines
Power Management
Interrupt Sources
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
163
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