AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 714

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.20.7.3
40.20.7.4
40.20.7.5
40.20.8
40.20.8.1
40.20.8.2
40.20.8.3
None.
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1.
Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled
before disabling the TWI.
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit
rising in the TWI_SR, the NACK bit is not set.
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission
is not completed.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR.
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is cor-
rupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if
this occurs.
The user must be sure that received data is read before transmitting any new data.
The Hardware Handshake does not work at speeds higher than 750 kbauds.
None.
When Hardware Handshaking is used and if CTS goes low near the end of the starting bit, a character can be lost.
CTS must not go low during a time slot occurring between 2 Master Clock periods before the starting bit and 16
Master Clock periods after the rising edge of the starting bit.
If CTS switches from 0 to 1 during the TX of a character and if the holding register (US_THR) is not empty, the con-
tent of US_THR will also be transmitted.
Don't use the PDC in transmit mode and do not fill US_THR before TXEMPTY is set at 1.
Universal Synchronous Asynchronous Receiver Transmitter (USART)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
USART: CTS in Hardware Handshaking
TWI: Disabling Does not Operate Correctly
TWI: NACK Status Bit Lost
TWI: Possible Receive Holding Register Corruption
USART: Hardware Handshake
USART: Hardware Handshaking – Two Characters Sent
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
714