AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 43
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Part Number:
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101
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11.2.4.1
11.2.4.2
Table 11-1.
Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the
processor.
All exceptions have banked registers for R14 and R13.
After an exception, R14 holds the return address for exception processing. This address is used to return after the
exception is processed, as well as to address the instruction that caused the exception.
R13 is banked across exception modes to provide each exception handler with a private stack pointer.
The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save
these registers.
A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers.
System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of
exceptions.
All other processor states are held in status registers. The current operating processor status is in the Current Pro-
gram Status Register (CPSR). The CPSR holds:
User and
System Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
PC
CPSR
• four ALU flags (Negative, Zero, Carry, and Overflow)
Modes and Exception Handling
Status Registers
ARM7TDMI ARM Modes and Registers Layout
Supervisor
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_SVC
R14_SVC
PC
CPSR
SPSR_SVC
Abort Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_ABORT
R14_ABORT
PC
CPSR
SPSR_ABORT
Undefined
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_UNDEF
R14_UNDEF
PC
CPSR
SPSR_UNDEF
Interrupt
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_IRQ
R14_IRQ
PC
CPSR
SPSR_IRQ
Mode-specific banked registers
SAM7S Series [DATASHEET]
Fast Interrupt
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
PC
CPSR
SPSR_FIQ
6175M–ATARM–26-Oct-12
43
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