AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 649

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.11.5.3
40.11.6
40.11.6.1
40.11.6.2
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V and 25 µA at
1.8V.
I Leakage
It is recommended to use an external pull-up if needed.
When NRST or PA0-PA16 and or PA21-PA31 are set as digital inputs with pull-up enabled, driving the I/O with an
output impedance higher than 500 ohms may not drive the I/O to a logical zero.
Output impedance must be lower than 500 ohms.
Under certain rare circumstances, when CSS = 00 in PMC_MCKR, and PA1 is set as an input and a transition
occurs on PA1, device malfunction might occur.
Do not transition PA1 as an input when CSS = 00 in PMC_MCKR.
Under certain rare circumstances, reprogramming the CSS value in the PMC_MCKR register (i.e switching the
main clock source) might generate malfunction of the device if the following two actions occur simultaneously.
Note:
When changing CSS in the PMC_MCKR to switch from
Ensure that the processor is executing out of SRAM and ensure no transition occurs on PA1, either as an input or
output, starting from writing to the PMC_MCKR register until MCKRDY = 1.
Parameter
I Leakage at 3,3V
I Leakage at 1.8V
1. Switching from:
2. Program code is being executed out of flash, or a transition is occurring on PA1, either as an input or
Power Management Controller (PMC)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
And
Problem Fix/Workaround
PIO: Drive Low NRST, PA0-PA16 and PA21-PA31
PMC: Slow Clock Selected in PMC and a Transition Occurs on PA1
PMC: Programming CSS in PMC_MCKR Register
– PLL Clock to Slow Clock or
– PLL Clock to Main Clock or
– Main Clock to PLL Clock or
– Main Clock to Slow Clock
output.
– PLL Clock to Slow Clock or
– PLL Clock to Main Clock or
– Main Clock to PLL Clock or
– Main Clock to Slow Clock
This issue does not occur when transitioning from slow clock to main clock or from slow clock to PLL clock.
Typ
2.5
1
µA
µA
Max
45
25
µA
µA
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
649