AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 65

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

13.3.5
13.3.6
The Reset State Manager manages the following priorities between the different reset sources, given in descend-
ing order:
Particular cases are listed below:
The Reset Controller status register (RSTC_SR) provides several status fields:
• Power-up Reset
• Brownout Reset
• Watchdog Reset
• Software Reset
• User Reset
• When in User Reset:
• When in Software Reset:
• When in Watchdog Reset:
• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software
• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This
• BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It
Reset State Priorities
Reset Controller Status Register
reset should be performed until the end of the current one. This bit is automatically cleared at the end of the
current software reset.
edge.
transition is also detected on the Master Clock (MCK) rising edge (see
disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the
URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the
interrupt.
triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR
register resets the BODSTS bit and clears the interrupt.
– A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.
– A software reset is impossible, since the processor reset is being activated.
– A watchdog event has priority over the current state.
– The NRST has no effect.
– The processor reset is active and so a Software Reset cannot be programmed.
– A User Reset cannot be entered.
Figure
SAM7S Series [DATASHEET]
13-9). If the User Reset is
6175M–ATARM–26-Oct-12
65