AT91SAM9G20B-CU Atmel, AT91SAM9G20B-CU Datasheet
AT91SAM9G20B-CU
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AT91SAM9G20-CU
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AT91SAM9G20B-CU Summary of contents
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... Mode for General Purpose 2-wire UART Serial Communication ® ® ARM Thumb Processor ® Technology for Java ® Acceleration AT91 ARM Thumb ® Microcontrollers AT91SAM9G20 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6384DS–ATARM–13-Jan-10 ...
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Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter • Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock • Real-time Timer (RTT) – 32-bit Free-running Backup Counter Running at ...
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Description The AT91SAM9G20 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a USB Host control- ...
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AT91SAM9G20 Block Diagram Figure 2-1. AT91SAM9G20 Block Diagram AT91SAM9G20 Summary 4 Filter Filter 6384DS–ATARM–13-Jan-10 ...
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Signal Description Table 3-1. Signal Description List (Continued) Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP Peripherals I/O Lines Power Supply VDDBU Backup I/O Lines Power Supply VDDANA Analog Power Supply VDDPLL PLL Power Supply VDDOSC Oscillator ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NRST Microcontroller Reset TST Test Mode Select BMS Boot Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ2 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NANDCS NAND Flash Chip Select NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable NANDALE NAND Flash Address Latch Enable NANDCLE NAND Flash Command Latch Enable SDCK SDRAM Clock SDCKE ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A TIOBx TC Channel x I/O Line B SPIx_MISO Master In Slave Out SPIx_MOSI Master Out Slave In ...
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Table 3-1. Signal Description List (Continued) Signal Name Function ISI_D0-ISI_D11 Image Sensor Data ISI_MCK Image Sensor Reference Clock ISI_HSYNC Image Sensor Horizontal Synchro ISI_VSYNC Image Sensor Vertical Synchro ISI_PCK Image Sensor Data clock AD0-AD3 Analog Inputs ADVREF Analog Positive Reference ...
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LFBGA Pinout Table 4-1. Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 CFIOW/NBS3/NWR3 D5 A2 NBS0/ NWR2/NBS2/ A11 D10 A7 A13 D11 A8 BA0/A16 D12 A9 ...
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TFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9G20 Mechanical Charac- teristics” of the product datasheet. Figure 4-2. 6384DS–ATARM–13-Jan-10 shows the orientation of the 247-ball TFBGA package. 247-ball TFBGA Package (Bottom View) ...
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TFBGA Package Pinout Table 4-2. Pinout for 247-ball TFBGA Package Pin Signal Name Pin A1 D13 F7 A2 D12 F8 A12 A9 F9 A14 A13 F10 A16 A20 F11 A18 A22 F12 A19 NANDOE F13 B1 D15 F14 ...
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Power Considerations 5.1 Power Supplies The AT91SAM9G20 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V nominal. • VDDIOM ...
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I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven VDDIOP, and have no pull-up resistor. The JTAGSEL pin is ...
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Processor and Architecture 7.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • ...
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Round-Robin Arbitration, either with no default master, last accessed default master • Burst Management – Breaking with Slot Cycle Limit Support – Undefined Burst Length Support • One Address Decoder provided per Master – Three different slaves may be ...
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Masters to Slaves Access All the Masters can normally access all the Slaves. However, some paths do not make sense, like as example allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or ...
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SPI0 Transmit Channel – SSC Transmit Channel – TWI Receive Channel – DBGU Receive Channel – USART5 Receive Channel – USART4 Receive Channel – USART3 Receive Channel – USART2 Receive Channel – USART1 Receive Channel – USART0 Receive Channel ...
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Memories Figure 8-1. AT91SAM9G20 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI Chip Select ...
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A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space ...
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When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: The AT91SAM9G20 matrix manages a boot memory that depends on ...
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External Memories The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256-Mbyte memory area assigned. Refer to the memory map in 8.2.1 External Bus Interface • Integrates three External Memory Controllers – ...
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Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – ...
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System Controller Block Diagram Figure 9-1. AT91SAM9G20 System Controller Block Diagram irq0-irq2 periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSCSEL SLOW XIN32 CLOCK OSC ...
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Reset Controller • Based on two Power-on-Reset cell – one on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software • Controls the internal resets and ...
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Figure 9-2. 9.5 Power Management Controller • Provides: – the Processor Clock PCK – the Master Clock MCK, in particular to the Matrix and the memory interfaces.The – the USB Device Clock UDPCK – independent peripheral clocks, typically at the ...
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Figure 9-3. 9.6 Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real Time OS or Linux 9.7 Watchdog Timer • 16-bit key-protected only-once-Programmable Counter • ...
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... Two-pin UART – Debug Communication Channel (DCC) support • Two-pin UART – Implemented features are 100% compatible with the standard Atmel – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – ...
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Peripherals 10.1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map ...
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Table 10-1. Peripheral Note: Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. The ADC clock is auto- matically started for the first conversion. In Sleep ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 SPI0_MISO PA1 SPI0_MOSI PA2 SPI0_SPCK PA3 SPI0_NPCS0 PA4 RTS2 PA5 CTS2 PA6 MCDA0 PA7 MCCDA PA8 MCCK PA9 MCDA1 PA10 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A Peripheral B PB0 SPI1_MISO TIOA3 PB1 SPI1_MOSI TIOB3 PB2 SPI1_SPCK TIOA4 PB3 SPI1_NPCS0 TIOA5 PB4 TXD0 PB5 RXD0 PB6 TXD1 TCLK1 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 PC1 PC2 PC3 PC4 A23 PC5 A24 PC6 TIOB2 PC7 TIOB1 PC8 NCS4/CFCS0 PC9 NCS5/CFCS1 PC10 A25/CFRNW PC11 NCS2 PC12 ...
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Embedded Peripherals 10.4.1 Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, ...
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by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Optional modem signal management DTR-DSR-DCD-RI – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with ...
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Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Each block contains two global registers that act on all three TC Channels Note: 10.4.6 Multimedia Card Interface • One double-channel MultiMedia Card Interface ...
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Ethernet 10/100 MAC • Compatibility with IEEE Standard 802.3 • 10 and 100 MBits per second data throughput capability • Full- and half-duplex operations • MII or RMII interface to the physical layer • Register Interface to address, data, ...
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Pacakge Drawing 11.1 217-ball LFBA Package Figure 11-1. 217-ball LFBGA Package Drawing AT91SAM9G20 Summary 38 6384DS–ATARM–13-Jan-10 ...
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TFBGA Package Figure 11-2. 247-ball TFBGA Package Drawing 6384DS–ATARM–13-Jan-10 AT91SAM9G20 Summary 39 ...
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... AT91SAM9G20 Ordering Information Table 12-1. AT91SAM9G20 Ordering Information MRL A Ordering Code MRL B Ordering Code AT91SAM9G20-CU AT91SAM9G20B-CU – AT91SAM9G20B-CFU AT91SAM9G20 Summary 40 Package Package Type Temperature Operating Range BGA217 Green BGA247 Green Industrial -40°C to 85°C Industrial -40°C to 85°C 6384DS–ATARM–13-Jan-10 ...
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Revision History Doc. Rev Comments 6348DS Section 5. “Power Considerations”, removed subsection: “Power Consumption Section 6. “I/O Line Considerations”, removed subsection: Slow Clock Selection 6348CS “Features” , Section 4.3 “247-ball TFBGA Package Pinout”, added 247-ball TFBGA package information. Section 10.4.6 ...
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