AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 189

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

24.3.5
24.4
24.4.1
24.4.2
The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the
external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the
product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the
MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly.
Divider and PLL Block
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must
respect the PLL minimum input frequency when programming the divider.
Figure 24-3
Figure 24-3. Divider and PLL Block Diagram
The PLL requires connection to an external second-order filter through the PLLRC pin.
matic of these filters.
Figure 24-4. PLL Capacitors and Resistors
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input fre-
quency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal
overshoot and startup time.
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the cor-
responding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the
corresponding PLL input clock is set to 0.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the
respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal
Main Oscillator Bypass
PLL Filter
Divider and Phase Lock Loop Programming
shows the block diagram of the divider and PLL block.
MAINCK
SLCK
C2
Divider
DIV
C1
R
PLLRC
GND
PLLCOUNT
Counter
PLLRC
PLL
MUL
PLL
PLL
OUT
SAM7S Series [DATASHEET]
LOCK
PLLCK
Figure 24-4
6175M–ATARM–26-Oct-12
shows a sche-
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