AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 74

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm
Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its
maximum value, corresponding to 0xFFFF_FFFF, after a reset.
The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to
start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow
Clock equal to 32.768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed
value. This also resets the 32-bit counter.
Note:
Figure 14-2. RTT Counting
Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):
1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles
after the write of the RTTRST bit in the RTT_MR register.
2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status
Register).
RTTINC (RTT_SR)
ALMS (RTT_SR)
APB Interface
RTPRES - 1
Prescaler
MCK
RTT
0
0
...
APB cycle
ALMV-1
ALMV
read RTT_SR
ALMV+1
SAM7S Series [DATASHEET]
ALMV+2
APB cycle
6175M–ATARM–26-Oct-12
ALMV+3
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