AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 138

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

20.3.4
Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address
field and a read/write bit. The data to be written is scanned into the 32-bit data field with the address of the register
to the 5-bit address field and 1 to the read/write bit. A register is read by scanning its address into the address field
and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data.
Refer to the ARM7TDMI reference manuel for more information on Comm channel operations.
Figure 20-8. TAP 8-bit DR Register
A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE 1149.1 for more
details on JTAG operations.
The write handshake is done by polling the Debug Comms Control Register until the R bit is cleared. Once cleared,
data can be written to the Debug Comms Data Register.
The read handshake is done by polling the Debug Comms Control Register until the W bit is set. Once set, data
can be read in the Debug Comms Data Register.
Several commands on the Flash memory are available. These commands are summarized in
126. Commands are run by the programmer through the serial interface that is reading and writing the Debug
Comms Registers.
• The address of the Debug Comms Control Register is 0x04.
• The address of the Debug Comms Data Register is 0x05.
Device Operations
The Debug Comms Control Register is read-only and allows synchronized handshaking between the processor
and the debugger.
– Bit 1 (W): Denotes whether the programmer can read a data through the Debug Comms Data Register.
– Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data Register. If R
If the device is busy W = 0, then the programmer must poll until W = 1.
= 1, data previously placed there through the scan chain has not been collected by the device and so
the programmer must wait.
TDI
r/w
4
Address
Decoder
Address
5
0
31
Debug Comms Control Register
Debug Comms Data Register
Data
32
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
0
Table 20-3 on page
TDO
138