AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 508

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 35-5. Setup Transaction Followed by a Data OUT Transaction
35.5.2.2
35.5.2.3
USB
Bus Packets
RXSETUP Flag
RX_Data_BKO
(UDP_CSRx)
FIFO (DPR)
Content
Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data
from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-
pong attributes.
To perform a Data IN transaction using a non ping-pong endpoint:
After the last packet has been sent, the application must clear TXCOMP once this has been set.
TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is
pending while TXCOMP is set.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Note:
1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_
2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte
3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s
4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP
5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or
6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s
7. The application clears the TXCOMP in the endpoint’s UDP_ CSRx.
Data IN Transaction
Using Endpoints Without Ping-pong Attributes
CSRx register (TXPKTRDY must be cleared).
values in the endpoint’s UDP_ FDRx register,
UDP_ CSRx register.
in the endpoint’s UDP_ CSRx register has been set. Then an interrupt for the corresponding endpoint is
pending while TXCOMP is set.
more byte values in the endpoint’s UDP_ FDRx register,
UDP_ CSRx register.
Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol
layer.
Setup
PID
Setup Received
XX
Data Setup
Set by USB Device
ACK
PID
Setup Handled by Firmware
Data OUT
PID
Interrupt Pending
Data Setup
Data OUT
Cleared by Firmware
NAK
PID
Data OUT
PID
SAM7S Series [DATASHEET]
Data Out Received
Set by USB
Device Peripheral
XX
Data OUT
6175M–ATARM–26-Oct-12
ACK
PID
Data
OUT
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