AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 16

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

7.
7.1
7.2
7.3
Processor and Architecture
ARM7TDMI Processor
Debug and Test Features
Memory Controller
RISC processor based on ARMv4T Von Neumann architecture
Two instruction sets
Three-stage pipeline architecture
Integrated EmbeddedICE
Debug Unit
IEEE1149.1 JTAG Boundary-scan on all digital pins
Bus Arbiter
Address decoder provides selection signals for
Abort Status Registers
Misalignment Detector
Remap Command
Embedded Flash Controller
Runs at up to 55 MHz, providing 0.9 MIPS/MHz
ARM
Thumb
Instruction Fetch (F)
Instruction Decode (D)
Execute (E)
Two watchpoint units
Test access port accessible through a JTAG protocol
Debug communication channel
Two-pin UART
Debug communication channel interrupt handling
Chip ID Register
Handles requests from the ARM7TDMI and the Peripheral DMA Controller
Three internal 1 Mbyte memory areas
One 256 Mbyte embedded peripheral area
Source, Type and all parameters of the access leading to an abort are saved
Facilitates debug by detection of bad pointers
Alignment checking of all data accesses
Abort generation in case of misalignment
Remaps the SRAM in place of the embedded non-volatile memory
Allows handling of dynamic exception vectors
Embedded Flash interface, up to three programmable wait states
Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states
Key-protected program, erase and lock/unlock sequencer
Single command for erasing, programming and locking operations
Interrupt generation in case of forbidden operation
®
high-performance 32-bit instruction set
®
high code density 16-bit instruction set
™
(embedded in-circuit emulator)
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
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