AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 59
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
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13.3.2.2
13.3.3
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out”
signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion
duration, named EXTERNAL_RESET_LENGTH, lasts 2
duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the
NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is
driven low for a time compliant with potential external devices connected on the system reset.
Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below
a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout
reset by asserting the bod_reset signal.
The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the cor-
responding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed.
Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when
RSTC_SR is read.
The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR.
At factory, the brownout reset is disabled.
Figure 13-3. Brownout Manager
Brownout Manager
NRST External Reset Control
bod_rst_en
brown_out
RSTC_SR
BODSTS
RSTC_MR
BODIEN
(ERSTL+1)
interrupt
sources
Other
Slow Clock cycles. This gives the approximate
SAM7S Series [DATASHEET]
bod_reset
rstc_irq
6175M–ATARM–26-Oct-12
59
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