AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 374
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Part Number:
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31.6.3.6
31.6.3.7
Figure 31-15. Timeguard Operations
Baud Rate
TXEMPTY
US_THR
TXRDY
Clock
Write
If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multi-
drop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the
parity bit at 0 and addresses are transmitted with the parity bit at 1.
If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high
and the transmitter is able to send a character with the parity bit high when the Control Register is written with the
SENDA bit at 1.
To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1.
The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte
written to US_THR is transmitted as an address. Any character written in US_THR without having written the com-
mand SENDA is transmitted normally with the parity at 0.
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This
idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR).
When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on
TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of
stop bits.
As illustrated in
a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the
timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard
transmission is completed as the timeguard is part of the current character being transmitted.
TXD
Multidrop Mode
Transmitter Timeguard
Start
Bit
D0
D1
Figure
D2
D3
31-15, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of
D4
D5
D6
D7
Parity
Bit
Stop
Bit
TG = 4
Start
Bit
D0
D1
D2
D3
D4
SAM7S Series [DATASHEET]
D5
D6
D7
Parity
Bit
6175M–ATARM–26-Oct-12
Stop
Bit
TG = 4
374
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