AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 755

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Version
6175I
Comments
Overview:
Section
Communication”
Section 7.4 ”Peripheral DMA
Section 9. ”System
Section 9.1.1 ”Brownout Detector and Power-on
Section 12.5.5 ”ID Code
Section 9.5 ”Debug
Rev B to the list.
ADC:
Figure 36-1 ”Analog-to-Digital Converter Block Diagram”
Section 36.6.2 ”ADC Mode
Section 36.5.5 ”Conversion
PMC:
“PMC Interrupt Enable Register”
Mask Register”
Section 25.7 ”Programming
devices having 12 peripheral clocks
Section 25.9.10 ”PMC Master Clock
Section 25.9 ”Power Management Controller (PMC) User
RSTC;
Section 13.3.4.4 ”Software
Electrical Characteristics:
Table 37-2, “DC
Table 37-4, “Brownout Detector
Table 37-19, “External Voltage Reference
Section 37.10.2 ”SSC
Ordering Information:
Table 39-1, “LQFP/QFN Ordering
versions.
Section 40. ”Errata”
Section 40.2 ”Errata Summary by Product and Revision or Manufacturing
Section 40-1 ”Errata Summary
Chip ID noted on products where no chip ID errata exists.
Section 40.18 ”SAM7S64 Errata - Revision B
Section 40.23 ”SAM7S32 Errata - Revision B
USART: XOFF Character Bad Behavior, removed from all revisions of the AT91SAM7S series components.
”Features”,
, LOCKU and UOSCS removed from bit fields in register tables.
Characteristics”, CMOS conditions added to I
Controller”,
Unit”, the list;
“Debug Unit (DBGU)”
Characteristics”, added to datasheet.
Register”, added “The JTAG ID is used in the IEEE 1149.1 JTAG Boundary Scan.”
Reset”; updated list with details on PERRST and PROCRST.
Register”, updated the formula on bit description:
Triggers”, update to the third paragraph detailing hardware trigger.
Sequence”,
Controller”, added list of PDC priorities.
Table”, added to Errata.
Figure 9-1
Characteristics”, V
,
“Chip ID Registers”
“PMC Interrupt Disable Register”
Information”, Updated product ordering information by MRL A and MRL B
Register”, MDIV removed from bit fields in register table.
Step6 “Enabling Peripheral
and
Input”, added ADVREF Input w/conditions “8-bit resolution mode”.
updated with
Parts”, added to Errata.
Parts”, removed errata for NVM and Voltage Regulator.
Figure 9-2
Reset”, fourth paragraph reduced.
BOT
, chip IDs updated, added SAM7S32 Rev B and SAM7S64
conditions = Falling edge.
“Mode for General Purpose 2-wire UART Serial
VDDANA replaced by VDDIN. PMC added to figure
RTT is reset by “power_on_reset”.
Interface”, added PMC_PCK2 to Register Mapping.
O
for V
,
Clocks”, AT91SAM7S512 grouped with
OL
“PMC Status Register”
and V
Number”, added to Errata.
OH
“SHTIM: Sample & Hold Time”
.
SAM7S Series [DATASHEET]
,
“PMC Interrupt
6175M–ATARM–26-Oct-12
.
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