AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 341

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

30.9.5.4
Figure 30-27. Clock Synchronization in Read Mode
Notes:
TWI_THR
TXCOMP
SVREAD
Clock Synchronization in Read Mode
SCLWS
SVACC
TXRDY
TWCK
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emis-
sion/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching
mechanism is implemented.
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected.
It is tied low until the shift register is loaded.
Figure 30-27 on page 341
1. TXRDY is reset when data has been written in the TWI_TH to the shift register and set when this data has been acknowl-
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
3. SCLWS is automatically set when the clock synchronization mechanism is started.
edged or non acknowledged.
SADR.
Clock Synchronization
1
2
S
S
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
As soon as a START is detected
SADR
DATA0
DATA0
R
describes the clock synchronization in Read mode.
Write THR
A
1
DATA0
A
DATA1
DATA1
CLOCK is tied low by the TWI
as long as THR is empty
A
XXXXXXX
2
DATA2
SAM7S Series [DATASHEET]
DATA2
Ack or Nack from the master
NA
6175M–ATARM–26-Oct-12
S
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