AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 107

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

19.2.2
Figure 19-2. Code Read Optimization in Thumb Mode for FWS = 0
Note:
Figure 19-3. Code Read Optimization in Thumb Mode for FWS = 1
Note:
ARM Request (16-bit)
ARM Request (16-bit)
Data To ARM
Data To ARM
Buffer (32 bits)
Flash Access
Buffer (32 bits)
Flash Access
Master Clock
Master Clock
An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added in order to start
access at following address during the second read, thus increasing performance when the processor is running in
Thumb mode (16-bit instruction set). See
This optimization concerns only Code Fetch and not Data.
The read operations can be performed with or without wait state. Up to 3 wait states can be programmed in the
field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see
Defining FWS to be 0 enables the single-cycle access of the embedded Flash.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded
Flash wraps around the address space and appears to be repeated within it.
Code Fetch
When FWS is equal to 0, all accesses are performed in a single-cycle access.
When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for the
first one).
Code Fetch
Read Operations
@Byte 0
@Byte 0
1 Wait State Cycle
Bytes 0-3
@Byte 2
Bytes 0-1
Bytes 0-3
@Byte 2
Bytes 4-7
@Byte 4
Bytes 0-3
Bytes 2-3
Bytes 0-1
1 Wait State Cycle
Figure
Bytes 4-5
@Byte 6
@Byte 4
Bytes 2-3
19-2,
Bytes 4-7
Bytes 4-7
Bytes 0-3
Figure 19-3
Bytes 8-11
@Byte 6
@Byte 8
Bytes 6-7
Bytes 4-5
1 Wait State Cycle
and
Bytes 8-9
@Byte 10
@Byte 8
Bytes 6-7
Figure
“MC Flash Mode Register” on page
Bytes 8-11
Bytes 8-11
Bytes 4-7
SAM7S Series [DATASHEET]
19-4.
Bytes 12-15
Bytes 10-11
@Byte 10
@Byte 12
Bytes 8-9
1 Wait State Cycle
6175M–ATARM–26-Oct-12
Bytes 12-13
Bytes 10-11
@Byte 12
@Byte 14
Bytes 12-15
Bytes 8-11
Bytes 12-15
Bytes 16-19
Bytes 12-13
Bytes 14-15
@Byte 14
@Byte 16
115).
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