AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 484

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

34.5.2
34.5.2.1
34.5.2.2
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true
when the PWM master clock is turned off through the Power Management Controller.
Figure 34-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of three blocks:
The different properties of output waveforms are:
• A clock selector which selects one of the clocks provided by the clock generator described in
• An internal counter clocked by the output of the clock selector. This internal counter is incremented or
• A comparator used to generate events according to the internal counter value. It also computes the PWMx
• the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock
• the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
PWM Channel
“PWM Clock Generator” on page
decremented according to the channel configuration and comparators events. The size of the internal counter is
16 bits.
output waveform according to the configuration.
generator described in the previous section. This channel parameter is defined in the CPRE field of the
PWM_CMRx register. This field is reset at 0.
- If the waveform is left aligned, then the output waveform period depends on the counter source clock and can
be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
(
--------------------------------- -
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(
-------------------------------------------- -
If the waveform is center aligned then the output waveform period depends on the counter source clock and can
be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
X
CRPD
Block Diagram
Waveform Properties
×
MCK
CPRD
MCK
inputs from
from clock
×
generator
APB bus
inputs
DIVA
)
)
or
(
------------------------------------------------ -
CRPD
Channel
Selector
Clock
MCK
×
DIVAB
483.
)
Counter
Internal
Comparator
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
PWMx
output waveform
Section 34.5.1
484