AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 151

no-image

AT91SAM7S256D-AU

Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet

Specifications of AT91SAM7S256D-AU

Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S256D-AU
Manufacturer:
ATMEL
Quantity:
101
Part Number:
AT91SAM7S256D-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7S256D-AU-999
Manufacturer:
Atmel
Quantity:
10 000
22. Peripheral DMA Controller (PDC)
22.1
22.2
Overview
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART,
USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor
intervention and removes the processor interrupt-handling overhead. This significantly reduces the number of
clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and
makes it more power efficient.
The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral. One channel in
the pair is dedicated to the receiving channel and one to the transmitting channel of each UART, USART, SSC and
SPI.
The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains:
The peripheral triggers PDC transfers using transmit and receive signals. When the programmed data is trans-
ferred, an end of transfer interrupt is generated by the corresponding peripheral.
Block Diagram
Figure 22-1. Block Diagram
• two 32-bit memory pointer registers (send and receive)
• two 16-bit transfer count registers (send and receive)
• two 32-bit registers for next memory pointer (send and receive)
• two 16-bit registers for next transfer count (send and receive)
Peripheral
Control
THR
RHR
Status & Control
PDC Channel 0
PDC Channel 1
Peripheral DMA Controller
Control
SAM7S Series [DATASHEET]
Controller
Memory
6175M–ATARM–26-Oct-12
151

Related parts for AT91SAM7S256D-AU