HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 99

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.1.3
Before exception handling starts, the exception handling vector table must be set in memory. The
exception handling vector table stores the start addresses of exception handling routines. (The
reset exception handling table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets. The
vector table addresses are calculated from these vector numbers and vector table address offsets.
During exception handling, the start addresses of the exception handling routines are fetched from
the exception handling vector table that is indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3
Exception Handling Source
Power-on reset
H-UDI reset
(Reserved by system)
General illegal instruction
(Reserved by system)
Illegal slot instruction
(Reserved by system)
CPU address error
(Reserved by system)
Interrupt
(Reserved by system)
Exception Handling Vector Table
Vector Numbers and Vector Table Address Offsets
PC
SP
NMI
User break
H-UDI
0
1
2
5
7
9
10
11
12
13
14
Vector Number
3
4
6
8
31
:
Vector Table Address Offset
H'00000000 to H'00000003
H'00000004 to H'00000007
H'00000008 to H'0000000B
H'0000000C to H'0000000F
H'00000010 to H'00000013
H'00000014 to H'00000017
H'00000018 to H'0000001B
H'0000001C to H'0000001F
H'00000020 to H'00000023
H'00000024 to H'00000027
H'00000028 to H'0000002B
H'0000002C to H'0000002F
H'00000030 to H'00000033
H'00000034 to H'00000037
H'00000038 to H'0000003B
H'0000007C to H'0000007F
Rev. 6.00 Jun. 12, 2007 Page 67 of 610
Section 5 Exception Handling
:
REJ09B0131-0600